moromarka

2008-01-24T06:11:00.000-08:00

Casino game

From Wikipedia, the free encyclopedia

Games available in most casinos are commonly called casino games. In a casino game, the players gamble casino chips on various possible random outcomes or combinations of outcomes. Casino games are available in online casinos, where permitted by law. Casino games can also be played outside of casinos for entertainment purposes, some on machines that simulate gambling.

House advantage or edge

Casino games generally provide a predictable long-term advantage to the casino, or "house", while offering the player the possibility of a large short-term payout. Some casino games have a skill element, where the player makes decisions; such games are called "random with a tactical element." While it is possible through skillful play to minimize the house advantage, it is extremely rare that a player has sufficient skill to completely eliminate his inherent long-term disadvantage (the house edge or house vigorish) in a casino game. Such a skill set would involve years of training, an extraordinary memory and numeracy, and/or acute visual or even aural observation, as in the case of wheel clocking in Roulette.

The player's disadvantage is a result of the casino not paying winning wagers according to the game's "true odds", which are the payouts that would be expected considering the odds of a wager either winning or losing. For example, if a game is played by wagering on the number that would result from the roll of one die, true odds would be 5 times the amount wagered since there is a 5 to 1 probability of any single number appearing. However, the casino may only pay 4 times the amount wagered for a winning wager.

The house edge (HE) or vigorish is defined as the casino profit expressed as a percentage of the player's original bet. (In games such as Blackjack or Spanish 21, the final bet may be several times the original bet, if the player double and splits.)

Example: In American Roulette, there are two zeroes and 36 non-zero numbers (18 red and 18 black). If a player bets $1 on red, his chance of winning $1 is therefore 18/38 and his chance of losing $1 (or winning -$1) is 20/38.

The player's expected value, EV = (18/38 x 1) + (20/38 x -1) = 18/38 - 20/38 = -2/38 = -5.26%. Therefore, the house edge is 5.26%. After 10 rounds, play $1 per round, the average house profit will be 10 x $1 x 5.26% = $0.53. Of course, it is not possible for the casino to win exactly 53 cents; this figure is the average casino profit from each player if it had millions of players each betting 10 rounds at $1 per round.

The house edge of casino games vary greatly with the game. Keno can have house edges up to 25%, slot machines can have up to 15%, while most Australian Pontoon games have house edges between 0.3% and 0.4%.

The calculation of the Roulette house edge was a trivial exercise; for other games, this is not usually the case. Combinatorial analysis and/or computer simulation is necessary to complete the task.

In games which have a skill element, such as Blackjack or Spanish 21, the house edge is defined as the house advantage from optimal play (without the use of advanced techniques such as card counting), on the first hand of the shoe (the container that holds the cards). The set of the optimal plays for all possible hands is known as "basic strategy" and is highly dependent on the specific rules, and even the number of decks used. Good Blackjack and Spanish 21 games have house edges below 0.5%.

Standard deviation

The luck factor in a casino game is quantified using standard deviation (SD). The standard deviation of a simple game like Roulette can be calculated using the binomial distribution. In the binomial distribution, SD = sqrt (npq ), where n = number of rounds played, p = probability of winning, and q = probability of losing. The binomial distribution assumes a result of 1 unit for a win, and 0 units for a loss, rather than -1 units for a loss, which doubles the range of possible outcomes. Furthermore, if we flat bet at 10 units per round instead of 1 unit, the range of possible outcomes increases 10 fold. Therefore,

SD (Roulette, even-money bet) = 2b sqrt(npq ), where b = flat bet per round, n = number of rounds, p = 18/38, and q = 20/38.

For example, after 10 rounds at $1 per round, the standard deviation will be 2 x 1 x sqrt(10 x 18/38 x 20/38) = $3.16. After 10 rounds, the expected loss will be 10 x $1 x 5.26% = $0.53. As you can see, standard deviation is many times the magnitude of the expected loss.

The range is six times the standard deviation: three above the mean, and three below. Therefore, after 10 rounds betting $1 per round, your result will be somewhere between -$0.53 - 3 x $3.16 and -$0.53 + 3 x $3.16, i.e., between -$10.01 and $8.95. (There is still a 0.1% chance that your result will exceed a $8.95 profit, and a 0.1% chance that you will lose more than $10.01.) This demonstrates how luck can be quantified; we know that if we walk into a casino and bet $5 per round for a whole night, we are not going to walk out with $500.

The standard deviation for Pai Gow poker is the lowest out of all common casinos games. Many games, particularly slots, have extremely high standard deviations. As the size of the potential payouts increase, so does the standard deviation.

As the number of rounds increases, eventually, the expected loss will exceed the standard deviation, many times over. From the formula, we can see the standard deviation is proportional to the square root of the number of rounds played, while the expected loss is proportional to the number of rounds played. As the number of rounds increases, the expected loss increases at a much faster rate. This is why it is impossible for a gambler to win in the long term. It is the high ratio of short-term standard deviation to expected loss that fools gamblers into thinking that they can win.

It is important for a casino to know both the house edge and variance for all of their games. The house edge tells them what kind of profit they will make as percentage of turnover, and the variance tells them how much they need in the way of cash reserves. The mathematicians and computer programmers that do this kind of work are called gaming mathematicians and gaming analysts. Casinos do not have in-house expertise in this field, so outsource their requirements to experts in the gaming analysis field, such as Mike Shackleford, the "Wizard of Odds".

Categories of casino games

There are three general categories of casino games: table games, electronic gaming machines, and random number ticket games such as Keno and simulated racing. Gaming machines, such as slot machines and pachinko, are usually played by one player at a time and do not require the involvement of casino employees to play. Random number games are based upon the selection of random numbers, either from a computerized random number generator or from other gaming equipment. Random number games may be played at a table, such as Roulette, or through the purchase of paper tickets or cards, such as Keno or Bingo.

Troubleshooting Resources

2008-01-22T18:29:00.000-08:00

The web is full of information sources on computers, but frankly, not all of them are that great. To help you wade through the morass of choices, I've put together my picks for some of the most informative computer sites I've seen. You can start by checking out the Troubleshooting Guide available right here on EverythingComputers.com, which covers both PC- and Mac-related problems.

All of the sites listed on this page contain either answers to common computer problems or useful information about how different aspects of computers work--some even have both.

Knowledge is truly power when it comes to computers, so you may find that simply finding out how something really works can go a long way towards solving problems on your own. Good luck.

PC Hardware

PC Guide

This site is a tremendous trove of information with well-written explanations of PC technology, thorough troubleshooting procedures and step-by-step instructions for common PC updates and upgrades.

Tom's Hardware Guide

One of the Web's truly useful treasures, this site has tons of great information about PCs, CPUs, and virtually any kind of hardware you need to deal with. It's in desperate need of a good editor, but there's lots of good stuff.

System Optimization - PC Hardware and Performance Guide

Another really useful site with lots of great original material as well as links to other really good stuff all over the 'net.

The BIOS Survival Guide

If you have any questions about your computer's BIOS or its BIOS Setup program, this site is the definitive resource.

PC Operating Systems

Microsoft How-Tos

A complete reference list of very well put-together online resources that cover Windows 2000, XP, Office as well as general topics such as Networking, Security and so on. This page serves as the starting point to dive into any one of these topics at as deep a level as you could ever want to go. A goldmine of tech support info.

Windows XP Professional How-Tos

Straight from the source, this Microsoft TechNet site offers an amazing wealth of practical articles on how to do (and solve) all kinds of things under XP. If you use XP, you have to check this out.

Windows Support Center

A wonderful find, this site features an extensive collection of original support articles, links to other support sites, freeware utilities, registry patches and a great Shutdown Troubleshooter that's worth a visit in and of itself.

Resource Management

If you're trying to figure out Windows Resources really are and what all those programs running in the background of your PC really are and what they do, then you need to check this site out.

Windows Startup

This is another great site that has tips on getting around Windows startup problems and an even more extensive list of programs that run in the background.

TechSupport Alert

A great site that offers lots of very well-written "How-To" guides as well as links to many other excellent troubleshooting resources on the web. Good stuff.

Windows TechFiles

This site offers many well-written articles explaining some common but confusing Windows-related issues. The articles not only explain why the problem is happening, they also tell you how to fix them.

Windows 95 Annoyances/Windows 98 Annoyances

Ever been annoyed by some aspect of Windows 95 or 98? (Who hasn't?!) These cleverly named sites offer workarounds to lots of common and not-so-common problems. They've also got a special link to download TweakUI for Windows 98.

Windows Planet Tips/Tutorials

This slick, online magazine includes lots of useful tips and tutorials for Windows 95/98/2000 and NT users.

Windows 95 OSR2 FAQ

Ever wondered about new features included in Windows 95B, such as FAT32? This site has tons of great info on the subject, including directions on how to upgrade older versions of Windows 95 to OSR2.

Windows SuperGuide

A great collection of tips for Win95, 98 and NT put together by PC/Computing each year. I edited the 1995 version while working there.

Windows NT Resource Center

If you're running NT at home or at work, you'll want to look through this site's news, software and tips.

PC Software

Outlook Express 5 FAQ

A simple, straightforward site with the critical information you need on moving your Outlook Express 4 and 5 files between different computer as well as answers to other common questions.

PC Drivers

Frank Condron's World o' Windows

You'll find lots of drivers here, as well as interesting news about all the various flavors of Windows.

WinDrivers.Com

You'll find a growing collection of drivers here, as well as some useful troubleshooting tips for driver-related problems.

The Driver Zone

Looking for a driver for an old add-in card? Or maybe the latest version for several new cards? This is great resource, with lots of drivers that you can download for free.

FCC Product ID Database

Can't figure out who made a particular component in your PC? Just find the FCC ID number, type it into this database and you'll get the company's name and contact information.

Home Networking

Practically Networked

This site includes product reviews, tutorials and more on the burgeoning home networking/high-speed Internet access sharing market.

Internet Connection Sharing How-To Guide

A subsection of Microsoft's support site, this page and its related links has everything you'd ever want to know about the ICS features built into Windows 98 2nd Edition, Windows Millenium and Windows 2000.

DSL Reports

If you want info about DSL products and services, as well as advice on how to best take advantage of your DSL line, this site is a great resource.

CableModemInfo.Com

If, instead, cable modem is your access means of choice, here's an equally useful site.

PPPoE Hardware

If you've had to deal with the dreaded PPP over Ethernet protocol through your DSL or cable modem service, you'll be pleased to read this page's how-to articles and FAQs.

NAT White Paper

Trying to make sense of Network Address Translation and other shared Internet connection technologies? This explanatory page from VicomSoft's web site is bound to help.

Network Design and Research Center

If you need explanations of some more complex networking concepts, you'll find good information and good links here.

Networking White Papers

While this page sits on the LinkSys site and has some hype about their products, it's also got lots of articles that offer a great introduction to networking issues.

General Info

PC Webopedia
A very thorough, accurate online computer dictionary that not only offers well-written definitions of common (and not-so-common) technology-related terms, but also provides useful links related to the words you look up.
File Extensions
Ever try to figure out a file's type by looking at its three dot extension? If so, this site is for you. It's got a comprehensive listing of extensions with a brief description of what the different types of files are.
BugNet

If you're trying to find out whether an annoying problem you keep running into is really a bug in one of your programs (or even your hardware), then this is the place to go. These folks keep track of and report on all kinds of different bugs. Note that some of the info they provide is free while other portions require a paid subscription.

Graphics

The FontSite

Interesting articles about typography and other design issues, as well as lots of free fonts and other goodies make this a winner.

A few scanning tips

Wayne Fulton's guide to scanning offers great advice on how to buy and use scanners. Be sure to check out his very useful scanning tips articles.

"How to draw" free exercises for kids and child

2008-01-22T07:32:00.000-08:00

The big problem of drawing books is a boring description after description but not enough actual illustrations and clear drawings. You practically had to be a brain surgeon to figure it out. See this free online lessons. It is only pictures. No boring description! You can draw figures, pets and people perfectly in any position. Without a Model!

Drawing lessons

Fun animation
Good memory eidetic game
Eidetic game
Mnemonic game
Kids online games
Speed reading is not magic software
Free flash online games
Free online music games
How to draw a face.
Paint pictures online (part 01)
Paint pictures online (part 02). You do not need print this pictures. Paint it online.
Online paint game for boys.
draw Christmas pictures
draw dogs
draw Easter
draw engineering
draw Hellowen pictures
draw nature
draw princess
draw valentine day pictures
Fun kids games
How to draw animals
How to draw pictures using primitives
How to draw people
How to draw hero
How to do a... Do it with your child.
Print and paint pictures. Print this pictures. Kids like painting. My little doter like paint this pictures.
Online Bible Jig saw. Research bible and fun with this jig saw pictures for school kids.
Math games for children and kids
Fun kids games. Music games for schools children.
Alphabet letters A-Z paint online. Learn abc with this online games.
Articles about children
Check your face memory. free online exercises
Checkers games. Best logic games. Chess. Checkers. Reverse. Tic Tac Toe.

Simply drawing lessons:
Try to see skeleton of the object
Try to see the main idea (try to make a grotesque the nose for the pig, long legs for girl).
Think how head & Neck connected with.
Try to draw by left hand
Draw the figure upside down (topsy-turvy).
Draw any free time.
Try to make circles
Try to make parallel lines
Have a proportion

How to draw software. The best lesson from this site

The Site Map of How To Draw site.

Home Based Earnings

2008-01-22T07:08:00.000-08:00

Another site which gives you the garentee of earning online, well this one really pays. Why am so confident about this site, because i have got some cheques from this site. This site has written up every thing, you can know all the methods of earning, there are help pages, contact links, jobs link, and most of all it's having pages for web masters. All the methods of getting traffic to your websites are listed there. Also most of all there are online games for free, and the games run very well. you can even enjoy these games on a dial up internet connection. This is the most important thing about these online games flash games, the first time you load, it takes time, but from the next time it loads very quickly. smoth playing fames and means entertainment and use of time. think for yourself, play games on one hand and earn money from the other. no other site gives you the information as this site. here you get all the help and support which makes a new person start earning lots of money in minutes. also for those how want to create websites, for free and also for those who want a paid web solution, this is the perfect place. earning online is very easy but if you fall to wrong sites, you will never succed, so it's important to get the right sites to start with, that no only helps you from fraud, also makes you confidence into these things. once i thought that every site that says earn online dose pays, but actually it's not so, actually most of the site dose not pays at all. some of the sites will vanish one day and you will not every find a way to catch that site. perhaps that why i suggest you to join only free to join sites. all the links in that site are free to join, perhaps this is the most important am suggesting every one to this site.

2007-11-13T13:15:00.000-08:00

CPU" redirects here. For other uses, see CPU (disambiguation).

Die of an Intel 80486DX2 microprocessor (actual size: 12×6.75 mm) in its packaging

A Central Processing Unit (CPU), or sometimes just processor, is a description of a certain class of logic machines that can execute computer programs. This broad definition can easily be applied to many early computers that existed long before the term "CPU" ever came into widespread usage. However, the term itself and its initialism have been in use in the computer industry at least since the early 1960s (Weik 1961). The form, design and implementation of CPUs have changed dramatically since the earliest examples, but their fundamental operation has remained much the same.

Early CPUs were custom-designed as a part of a larger, usually one-of-a-kind, computer. However, this costly method of designing custom CPUs for a particular application has largely given way to the development of mass-produced processors that are suited for one or many purposes. This standardization trend generally began in the era of discrete transistor mainframes and minicomputers and has rapidly accelerated with the popularization of the integrated circuit (IC). The IC has allowed increasingly complex CPUs to be designed and manufactured in very small spaces (on the order of millimeters). Both the miniaturization and standardization of CPUs have increased the presence of these digital devices in modern life far beyond the limited application of dedicated computing machines. Modern microprocessors appear in everything from automobiles to cell phones to children's toys.

[hide]

[edit] History of CPUs

Main article: History of general purpose CPUs

EDVAC, one of the first electronic stored program computers.

Prior to the advent of machines that resemble today's CPUs, computers such as the ENIAC had to be physically rewired in order to perform different tasks. These machines are often referred to as "fixed-program computers," since they had to be physically reconfigured in order to run a different program. Since the term "CPU" is generally defined as a software (computer program) execution device, the earliest devices that could rightly be called CPUs came with the advent of the stored-program computer.

The idea of a stored-program computer was already present during ENIAC's design, but was initially omitted so the machine could be finished sooner. On June 30, 1945, before ENIAC was even completed, mathematician John von Neumann distributed the paper entitled "First Draft of a Report on the EDVAC." It outlined the design of a stored-program computer that would eventually be completed in August 1949 (von Neumann 1945). EDVAC was designed to perform a certain number of instructions (or operations) of various types. These instructions could be combined to create useful programs for the EDVAC to run. Significantly, the programs written for EDVAC were stored in high-speed computer memory rather than specified by the physical wiring of the computer. This overcame a severe limitation of ENIAC, which was the large amount of time and effort it took to reconfigure the computer to perform a new task. With von Neumann's design, the program, or software, that EDVAC ran could be changed simply by changing the contents of the computer's memory.^[1]

While von Neumann is most often credited with the design of the stored-program computer because of his design of EDVAC, others before him such as Konrad Zuse had suggested similar ideas. Additionally, the so-called Harvard architecture of the Harvard Mark I, which was completed before EDVAC, also utilized a stored-program design using punched paper tape rather than electronic memory. The key difference between the von Neumann and Harvard architectures is that the latter separates the storage and treatment of CPU instructions and data, while the former uses the same memory space for both. Most modern CPUs are primarily von Neumann in design, but elements of the Harvard architecture are commonly seen as well.

Being digital devices, all CPUs deal with discrete states and therefore require some kind of switching elements to differentiate between and change these states. Prior to commercial acceptance of the transistor, electrical relays and vacuum tubes (thermionic valves) were commonly used as switching elements. Although these had distinct speed advantages over earlier, purely mechanical designs, they were unreliable for various reasons. For example, building direct current sequential logic circuits out of relays requires additional hardware to cope with the problem of contact bounce. While vacuum tubes do not suffer from contact bounce, they must heat up before becoming fully operational and eventually stop functioning altogether.^[2] Usually, when a tube failed, the CPU would have to be diagnosed to locate the failing component so it could be replaced. Therefore, early electronic (vacuum tube based) computers were generally faster but less reliable than electromechanical (relay based) computers. Tube computers like EDVAC tended to average eight hours between failures, whereas relay computers like the (slower, but earlier) Harvard Mark I failed very rarely (Weik 1961:238). In the end, tube based CPUs became dominant because the significant speed advantages afforded generally outweighed the reliability problems. Most of these early synchronous CPUs ran at low clock rates compared to modern microelectronic designs (see below for a discussion of clock rate). Clock signal frequencies ranging from 100 kHz to 4 MHz were very common at this time, limited largely by the speed of the switching devices they were built with.

[edit] Discrete transistor and IC CPUs

CPU, core memory, and external bus interface of an MSI PDP-8/I.

The design complexity of CPUs increased as various technologies facilitated building smaller and more reliable electronic devices. The first such improvement came with the advent of the transistor. Transistorized CPUs during the 1950s and 1960s no longer had to be built out of bulky, unreliable, and fragile switching elements like vacuum tubes and electrical relays. With this improvement more complex and reliable CPUs were built onto one or several printed circuit boards containing discrete (individual) components.

During this period, a method of manufacturing many transistors in a compact space gained popularity. The integrated circuit (IC) allowed a large number of transistors to be manufactured on a single semiconductor-based die, or "chip." At first only very basic non-specialized digital circuits such as NOR gates were miniaturized into ICs. CPUs based upon these "building block" ICs are generally referred to as "small-scale integration" (SSI) devices. SSI ICs, such as the ones used in the Apollo guidance computer, usually contained transistor counts numbering in multiples of ten. To build an entire CPU out of SSI ICs required thousands of individual chips, but still consumed much less space and power than earlier discrete transistor designs. As microelectronic technology advanced, an increasing number of transistors were placed on ICs, thus decreasing the quantity of individual ICs needed for a complete CPU. MSI and LSI (medium- and large-scale integration) ICs increased transistor counts to hundreds, then thousands.

In 1964 IBM introduced its System/360 computer architecture, which was used in a series of computers that could run the same programs with different speed and performance. This was significant at a time when most electronic computers were incompatible with one another, even those made by the same manufacturer. To facilitate this improvement, IBM utilized the concept of a microprogram (often called "microcode"), which still sees widespread usage in modern CPUs (Amdahl et al. 1964). The System/360 architecture was so popular that it dominated the mainframe computer market for the next few decades and left a legacy that is still continued by similar modern computers like the IBM zSeries. In the same year (1964), Digital Equipment Corporation (DEC) introduced another influential computer aimed at the scientific and research markets, the PDP-8. DEC would later introduce the extremely popular PDP-11 line that originally was built with SSI ICs but was eventually implemented with LSI components once these became practical. In stark contrast with its SSI and MSI predecessors, the first LSI implementation of the PDP-11 contained a CPU composed of only four LSI integrated circuits (Digital Equipment Corporation 1975).

Transistor-based computers had several distinct advantages over their predecessors. Aside from facilitating increased reliability and lower power consumption, transistors also allowed CPUs to operate at much higher speeds because of the short switching time of a transistor in comparison to a tube or relay. Thanks to both the increased reliability as well as the dramatically increased speed of the switching elements (which were almost exclusively transistors by this time), CPU clock rates in the tens of megahertz were obtained during this period. Additionally, while discrete transistor and IC CPUs were in heavy usage, new high-performance designs like SIMD (Single Instruction Multiple Data) vector processors began to appear. These early experimental designs later gave rise to the era of specialized supercomputers like those made by Cray Inc.

[edit] Microprocessors

Main article: Microprocessor

Intel 80486DX2 microprocessor in a ceramic PGA package

The introduction of the microprocessor in the 1970s significantly affected the design and implementation of CPUs. Since the introduction of the first microprocessor (the Intel 4004) in 1970 and the first widely used microprocessor (the Intel 8080) in 1974, this class of CPUs has almost completely overtaken all other central processing unit implementation methods. Mainframe and minicomputer manufacturers of the time launched proprietary IC development programs to upgrade their older computer architectures, and eventually produced instruction set compatible microprocessors that were backward-compatible with their older hardware and software. Combined with the advent and eventual vast success of the now ubiquitous personal computer, the term "CPU" is now applied almost exclusively to microprocessors.

Previous generations of CPUs were implemented as discrete components and numerous small integrated circuits (ICs) on one or more circuit boards. Microprocessors, on the other hand, are CPUs manufactured on a very small number of ICs; usually just one. The overall smaller CPU size as a result of being implemented on a single die means faster switching time because of physical factors like decreased gate parasitic capacitance. This has allowed synchronous microprocessors to have clock rates ranging from tens of megahertz to several gigahertz. Additionally, as the ability to construct exceedingly small transistors on an IC has increased, the complexity and number of transistors in a single CPU has increased dramatically. This widely observed trend is described by Moore's law, which has proven to be a fairly accurate predictor of the growth of CPU (and other IC) complexity to date.

While the complexity, size, construction, and general form of CPUs have changed drastically over the past sixty years, it is notable that the basic design and function has not changed much at all. Almost all common CPUs today can be very accurately described as von Neumann stored-program machines.

As the aforementioned Moore's law continues to hold true, concerns have arisen about the limits of integrated circuit transistor technology. Extreme miniaturization of electronic gates is causing the effects of phenomena like electromigration and subthreshold leakage to become much more significant. These newer concerns are among the many factors causing researchers to investigate new methods of computing such as the quantum computer, as well as to expand the usage of parallelism and other methods that extend the usefulness of the classical von Neumann model.

[edit] CPU operation

The fundamental operation of most CPUs, regardless of the physical form they take, is to execute a sequence of stored instructions called a program. Discussed here are devices that conform to the common von Neumann architecture. The program is represented by a series of numbers that are kept in some kind of computer memory. There are four steps that nearly all von Neumann CPUs use in their operation: fetch, decode, execute, and writeback.

Diagram showing how one MIPS32 instruction is decoded. (MIPS Technologies 2005)

The first step, fetch, involves retrieving an instruction (which is represented by a number or sequence of numbers) from program memory. The location in program memory is determined by a program counter (PC), which stores a number that identifies the current position in the program. In other words, the program counter keeps track of the CPU's place in the current program. After an instruction is fetched, the PC is incremented by the length of the instruction word in terms of memory units.^[3] Often the instruction to be fetched must be retrieved from relatively slow memory, causing the CPU to stall while waiting for the instruction to be returned. This issue is largely addressed in modern processors by caches and pipeline architectures (see below).

The instruction that the CPU fetches from memory is used to determine what the CPU is to do. In the decode step, the instruction is broken up into parts that have significance to other portions of the CPU. The way in which the numerical instruction value is interpreted is defined by the CPU's instruction set architecture (ISA).^[4] Often, one group of numbers in the instruction, called the opcode, indicates which operation to perform. The remaining parts of the number usually provide information required for that instruction, such as operands for an addition operation. Such operands may be given as a constant value (called an immediate value), or as a place to locate a value: a register or a memory address, as determined by some addressing mode. In older designs the portions of the CPU responsible for instruction decoding were unchangeable hardware devices. However, in more abstract and complicated CPUs and ISAs, a microprogram is often used to assist in translating instructions into various configuration signals for the CPU. This microprogram is sometimes rewritable so that it can be modified to change the way the CPU decodes instructions even after it has been manufactured.

Block diagram of a simple CPU

After the fetch and decode steps, the execute step is performed. During this step, various portions of the CPU are connected so they can perform the desired operation. If, for instance, an addition operation was requested, an arithmetic logic unit (ALU) will be connected to a set of inputs and a set of outputs. The inputs provide the numbers to be added, and the outputs will contain the final sum. The ALU contains the circuitry to perform simple arithmetic and logical operations on the inputs (like addition and bitwise operations). If the addition operation produces a result too large for the CPU to handle, an arithmetic overflow flag in a flags register may also be set (see the discussion of integer range below).

The final step, writeback, simply "writes back" the results of the execute step to some form of memory. Very often the results are written to some internal CPU register for quick access by subsequent instructions. In other cases results may be written to slower, but cheaper and larger, main memory. Some types of instructions manipulate the program counter rather than directly produce result data. These are generally called "jumps" and facilitate behavior like loops, conditional program execution (through the use of a conditional jump), and functions in programs.^[5] Many instructions will also change the state of digits in a "flags" register. These flags can be used to influence how a program behaves, since they often indicate the outcome of various operations. For example, one type of "compare" instruction considers two values and sets a number in the flags register according to which one is greater. This flag could then be used by a later jump instruction to determine program flow.

After the execution of the instruction and writeback of the resulting data, the entire process repeats, with the next instruction cycle normally fetching the next-in-sequence instruction because of the incremented value in the program counter. If the completed instruction was a jump, the program counter will be modified to contain the address of the instruction that was jumped to, and program execution continues normally. In more complex CPUs than the one described here, multiple instructions can be fetched, decoded, and executed simultaneously. This section describes what is generally referred to as the "Classic RISC pipeline," which in fact is quite common among the simple CPUs used in many electronic devices (often called microcontrollers^[clarify]).^[6]

[edit] Design and implementation

Main article: CPU design

Prerequisites
Computer architecture
Digital circuits

[edit] Integer range

The way a CPU represents numbers is a design choice that affects the most basic ways in which the device functions. Some early digital computers used an electrical model of the common decimal (base ten) numeral system to represent numbers internally. A few other computers have used more exotic numeral systems like ternary (base three). Nearly all modern CPUs represent numbers in binary form, with each digit being represented by some two-valued physical quantity such as a "high" or "low" voltage.^[7]

MOS 6502 microprocessor in a dual in-line package, an extremely popular 8-bit design.

Related to number representation is the size and precision of numbers that a CPU can represent. In the case of a binary CPU, a bit refers to one significant place in the numbers a CPU deals with. The number of bits (or numeral places) a CPU uses to represent numbers is often called "word size", "bit width", "data path width", or "integer precision" when dealing with strictly integer numbers (as opposed to floating point). This number differs between architectures, and often within different parts of the very same CPU. For example, an 8-bit CPU deals with a range of numbers that can be represented by eight binary digits (each digit having two possible values), that is, 2⁸ or 256 discrete numbers. In effect, integer size sets a hardware limit on the range of integers the software run by the CPU can utilize.^[8]

Integer range can also affect the number of locations in memory the CPU can address (locate). For example, if a binary CPU uses 32 bits to represent a memory address, and each memory address represents one octet (8 bits), the maximum quantity of memory that CPU can address is 2³² octets, or 4 GB (GiB). This is a very simple view of CPU address space, and many designs use more complex addressing methods like paging in order to locate more memory than their integer range would allow with a flat address space.

Higher levels of integer range require more structures to deal with the additional digits, and therefore more complexity, size, power usage, and general expense. It is not at all uncommon, therefore, to see 4- or 8-bit microcontrollers used in modern applications, even though CPUs with much higher range (such as 16, 32, 64, even 128-bit) are available. The simpler microcontrollers are usually cheaper, use less power, and therefore dissipate less heat, all of which can be major design considerations for electronic devices. However, in higher-end applications, the benefits afforded by the extra range (most often the additional address space) are more significant and often affect design choices. To gain some of the advantages afforded by both lower and higher bit lengths, many CPUs are designed with different bit widths for different portions of the device. For example, the IBM System/370 used a CPU that was primarily 32 bit, but it used 128-bit precision inside its floating point units to facilitate greater accuracy and range in floating point numbers (Amdahl et al. 1964). Many later CPU designs use similar mixed bit width, especially when the processor is meant for general-purpose usage where a reasonable balance of integer and floating point capability is required.

[edit] Clock rate

Main article: Clock rate

Most CPUs, and indeed most sequential logic devices, are synchronous in nature.^[9] That is, they are designed and operate on assumptions about a synchronization signal. This signal, known as a clock signal, usually takes the form of a periodic square wave. By calculating the maximum time that electrical signals can move in various branches of a CPU's many circuits, the designers can select an appropriate period for the clock signal.

This period must be longer than the amount of time it takes for a signal to move, or propagate, in the worst-case scenario. In setting the clock period to a value well above the worst-case propagation delay, it is possible to design the entire CPU and the way it moves data around the "edges" of the rising and falling clock signal. This has the advantage of simplifying the CPU significantly, both from a design perspective and a component-count perspective. However, it also carries the disadvantage that the entire CPU must wait on its slowest elements, even though some portions of it are much faster. This limitation has largely been compensated for by various methods of increasing CPU parallelism (see below).

However architectural improvements alone do not solve all of the drawbacks of globally synchronous CPUs. For example, a clock signal is subject to the delays of any other electrical signal. Higher clock rates in increasingly complex CPUs make it more difficult to keep the clock signal in phase (synchronized) throughout the entire unit. This has led many modern CPUs to require multiple identical clock signals to be provided in order to avoid delaying a single signal significantly enough to cause the CPU to malfunction. Another major issue as clock rates increase dramatically is the amount of heat that is dissipated by the CPU. The constantly changing clock causes many components to switch regardless of whether they are being used at that time. In general, a component that is switching uses more energy than an element in a static state. Therefore, as clock rate increases, so does heat dissipation, causing the CPU to require more effective cooling solutions.

One method of dealing with the switching of unneeded components is called clock gating, which involves turning off the clock signal to unneeded components (effectively disabling them). However, this is often regarded as difficult to implement and therefore does not see common usage outside of very low-power designs.^[10] Another method of addressing some of the problems with a global clock signal is the removal of the clock signal altogether. While removing the global clock signal makes the design process considerably more complex in many ways, asynchronous (or clockless) designs carry marked advantages in power consumption and heat dissipation in comparison with similar synchronous designs. While somewhat uncommon, entire CPUs have been built without utilizing a global clock signal. Two notable examples of this are the ARM compliant AMULET and the MIPS R3000 compatible MiniMIPS. Rather than totally removing the clock signal, some CPU designs allow certain portions of the device to be asynchronous, such as using asynchronous ALUs in conjunction with superscalar pipelining to achieve some arithmetic performance gains. While it is not altogether clear whether totally asynchronous designs can perform at a comparable or better level than their synchronous counterparts, it is evident that they do at least excel in simpler math operations. This, combined with their excellent power consumption and heat dissipation properties, makes them very suitable for embedded computers (Garside et al. 1999).

[edit] Parallelism

Main article: Parallel computing

Model of a subscalar CPU. Notice that it takes fifteen cycles to complete three instructions.

The description of the basic operation of a CPU offered in the previous section describes the simplest form that a CPU can take. This type of CPU, usually referred to as subscalar, operates on and executes one instruction on one or two pieces of data at a time.

This process gives rise to an inherent inefficiency in subscalar CPUs. Since only one instruction is executed at a time, the entire CPU must wait for that instruction to complete before proceeding to the next instruction. As a result the subscalar CPU gets "hung up" on instructions which take more than one clock cycle to complete execution. Even adding a second execution unit (see below) does not improve performance much; rather than one pathway being hung up, now two pathways are hung up and the number of unused transistors is increased. This design, wherein the CPU's execution resources can operate on only one instruction at a time, can only possibly reach scalar performance (one instruction per clock). However, the performance is nearly always subscalar (less than one instruction per cycle).

Attempts to achieve scalar and better performance have resulted in a variety of design methodologies that cause the CPU to behave less linearly and more in parallel. When referring to parallelism in CPUs, two terms are generally used to classify these design techniques. Instruction level parallelism (ILP) seeks to increase the rate at which instructions are executed within a CPU (that is, to increase the utilization of on-die execution resources), and thread level parallelism (TLP) purposes to increase the number of threads (effectively individual programs) that a CPU can execute simultaneously. Each methodology differs both in the ways in which they are implemented, as well as the relative effectiveness they afford in increasing the CPU's performance for an application.^[11]

[edit] Instruction level parallelism

Main articles: Instruction pipelining and Superscalar

Basic five-stage pipeline. In the best case scenario, this pipeline can sustain a completion rate of one instruction per cycle.

One of the simplest methods used to accomplish increased parallelism is to begin the first steps of instruction fetching and decoding before the prior instruction finishes executing. This is the simplest form of a technique known as instruction pipelining, and is utilized in almost all modern general-purpose CPUs. Pipelining allows more than one instruction to be executed at any given time by breaking down the execution pathway into discrete stages. This separation can be compared to an assembly line, in which an instruction is made more complete at each stage until it exits the execution pipeline and is retired.

Pipelining does, however, introduce the possibility for a situation where the result of the previous operation is needed to complete the next operation; a condition often termed data dependency conflict. To cope with this, additional care must be taken to check for these sorts of conditions and delay a portion of the instruction pipeline if this occurs. Naturally, accomplishing this requires additional circuitry, so pipelined processors are more complex than subscalar ones (though not very significantly so). A pipelined processor can become very nearly scalar, inhibited only by pipeline stalls (an instruction spending more than one clock cycle in a stage).

Simple superscalar pipeline. By fetching and dispatching two instructions at a time, a maximum of two instructions per cycle can be completed.

Further improvement upon the idea of instruction pipelining led to the development of a method that decreases the idle time of CPU components even further. Designs that are said to be superscalar include a long instruction pipeline and multiple identical execution units. ^{[Huynh 2003]} In a superscalar pipeline, multiple instructions are read and passed to a dispatcher, which decides whether or not the instructions can be executed in parallel (simultaneously). If so they are dispatched to available execution units, resulting in the ability for several instructions to be executed simultaneously. In general, the more instructions a superscalar CPU is able to dispatch simultaneously to waiting execution units, the more instructions will be completed in a given cycle.

Most of the difficulty in the design of a superscalar CPU architecture lies in creating an effective dispatcher. The dispatcher needs to be able to quickly and correctly determine whether instructions can be executed in parallel, as well as dispatch them in such a way as to keep as many execution units busy as possible. This requires that the instruction pipeline is filled as often as possible and gives rise to the need in superscalar architectures for significant amounts of CPU cache. It also makes hazard-avoiding techniques like branch prediction, speculative execution, and out-of-order execution crucial to maintaining high levels of performance. By attempting to predict which branch (or path) a conditional instruction will take, the CPU can minimize the number of times that the entire pipeline must wait until a conditional instruction is completed. Speculative execution often provides modest performance increases by executing portions of code that may or may not be needed after a conditional operation completes. Out-of-order execution somewhat rearranges the order in which instructions are executed to reduce delays due to data dependencies.

In the case where a portion of the CPU is superscalar and part is not, the part which is not suffers a performance penalty due to scheduling stalls. The original Intel Pentium (P5) had two superscalar ALUs which could accept one instruction per clock each, but its FPU could not accept one instruction per clock. Thus the P5 was integer superscalar but not floating point superscalar. Intel's successor to the Pentium architecture, P6, added superscalar capabilities to its floating point features, and therefore afforded a significant increase in floating point instruction performance.

Both simple pipelining and superscalar design increase a CPU's ILP by allowing a single processor to complete execution of instructions at rates surpassing one instruction per cycle (IPC).^[12] Most modern CPU designs are at least somewhat superscalar, and nearly all general purpose CPUs designed in the last decade are superscalar. In later years some of the emphasis in designing high-ILP computers has been moved out of the CPU's hardware and into its software interface, or ISA. The strategy of the very long instruction word (VLIW) causes some ILP to become implied directly by the software, reducing the amount of work the CPU must perform to boost ILP and thereby reducing the design's complexity.

[edit] Thread level parallelism

Another strategy of achieving performance is to execute multiple programs or threads in parallel. This area of research is known as parallel computing. In Flynn's taxonomy, this strategy is known as Multiple Instructions-Multiple Data or MIMD.

One technology used for this purpose was multiprocessing (MP). The initial flavor of this technology is known as symmetric multiprocessing (SMP), where a small number of CPUs share a coherent view of their memory system. In this scheme, each CPU has additional hardware to maintain a constantly up-to-date view of memory. By avoiding stale views of memory, the CPUs can cooperate on the same program and programs can migrate from one CPU to another. To increase the number of cooperating CPUs beyond a handful, schemes such as non-uniform memory access (NUMA) and Directory-based coherence protocols were introduced in the 1990s. SMP systems are limited to a small number of CPUs while NUMA systems have been built with thousands of processors. Initially, multiprocessing was built using multiple discrete CPUs and boards to implement the interconnect between the processors. When the processors and their interconnect are all implemented on a single silicon chip, the technology is known as a Multi-core microprocesor.

It was later recognized that finer-grain parallelism existed with a single program. A single program might have several threads (or functions) that could be executed separately or in parallel. Some of earliest examples of this technology was to consider Input/output processing such as Direct memory access as a separate thread from the computation thread. A more general approach to this technology was introduced in the 1970s when systems were designed to run multiple computation threads in parallel. This technology is known as multi-threading (MT). This approach is considered more cost-effective than multiprocessing, as only a small number of components within a CPU is replicated in order to support MT as opposed to the entire CPU in the case of MP. In MT, the execution units and the memory system including the caches are shared among multiple threads. The downside of MT is that the hardware support for multithreading is more visible to software than that of MP and thus supervisor software like operating systems have to undergo larger changes to support MT. One type of MT that was implemented is known as block multithreading, where one thread is executed until it is stalled waiting for data to return from external memory. In this scheme, the CPU would then quickly switch to another thread which is ready to run, the switch often done in one CPU clock cycle. Another type of MT is known as Simultaneous multithreading, where instructions of multiple threads are executed in parallel within one CPU clock cycle.

For several decades from the 1970s to early 2000s, the focus in designing high performance general purpose CPUs was largely on achieving high ILP through technologies such as pipelining, caches, superscalar execution, Out-of-order execution, etc. This trend culminated in large, power-hungry CPUs such as the Intel Pentium 4. By the early 2000s, CPU designers were thwarted from achieving higher performance from ILP techniques due to:

the growing disparity between CPU operating frequencies and main memory operating frequencies
the escalating CPU power dissipation that was needed for more esoteric ILP techniques

CPU designers then borrowed ideas from commercial computing markets such as transaction processing, where the aggregate performance of multiple programs, also known as throughput computing, was more important than the performance of a single thread or program.

This reversal of emphasis is evidenced by the proliferation of dual and multi core CMP designs and notably, Intel's newer designs resembling its less superscalar P6 architecture. Late designs in several processor families exhibit CMP, including the x86-64 Opteron and Athlon 64 X2, the SPARC UltraSPARC T1, IBM POWER4 and POWER5, as well as several video game console CPUs like the Xbox 360's triple-core PowerPC design.

[edit] Data parallelism

Main articles: Vector processor and SIMD

A less common but increasingly important paradigm of CPUs (and indeed, computing in general) deals with data parallelism. The processors discussed earlier are all referred to as some type of scalar device.^[13] As the name implies, vector processors deal with multiple pieces of data in the context of one instruction. This contrasts with scalar processors, which deal with one piece of data for every instruction. Using Flynn's taxonomy, these two schemes of dealing with data are generally referred to as SISD (single instruction, single data) and SIMD (single instruction, multiple data), respectively. The great utility in creating CPUs that deal with vectors of data lies in optimizing tasks that tend to require the same operation (for example, a sum or a dot product) to be performed on a large set of data. Some classic examples of these types of tasks are multimedia applications (images, video, and sound), as well as many types of scientific and engineering tasks. Whereas a scalar CPU must complete the entire process of fetching, decoding, and executing each instruction and value in a set of data, a vector CPU can perform a single operation on a comparatively large set of data with one instruction. Of course, this is only possible when the application tends to require many steps which apply one operation to a large set of data.

Most early vector CPUs, such as the Cray-1, were associated almost exclusively with scientific research and cryptography applications. However, as multimedia has largely shifted to digital media, the need for some form of SIMD in general-purpose CPUs has become significant. Shortly after floating point execution units started to become commonplace to include in general-purpose processors, specifications for and implementations of SIMD execution units also began to appear for general-purpose CPUs. Some of these early SIMD specifications like Intel's MMX were integer-only. This proved to be a significant impediment for some software developers, since many of the applications that benefit from SIMD primarily deal with floating point numbers. Progressively, these early designs were refined and remade into some of the common, modern SIMD specifications, which are usually associated with one ISA. Some notable modern examples are Intel's SSE and the PowerPC-related AltiVec (also known as VMX).^[14]

[hide] v • d • e CPU technologies
Microarchitecture	ISA · RISC · CISC · EPIC · VLIW · Harvard architecture · Von Neumann architecture
Pipelining	Superscalar · Out-of-order execution · Speculative execution · Multithreading · Multiprocessing
Components	ALU · FPU · Vector processor · SIMD · 32-bit/64-bit · Registers · Cache · ASIC · FPGA · DSP · Microcontroller · ASIP · SoC
Power conservation	Dynamic frequency scaling · Dynamic voltage scaling

[edit] See also

[edit] Notes

^ While EDVAC was designed a few years before ENIAC was built, ENIAC was actually retrofitted to execute stored programs in 1948, somewhat before EDVAC was completed. Therefore, ENIAC became a stored program computer before EDVAC was completed, even though stored program capabilities were originally omitted from ENIAC's design due to cost and schedule concerns.
^ Vacuum tubes eventually stop functioning in the course of normal operation due to the slow contamination of their cathodes that occurs when the tubes are in use. Additionally, sometimes the tube's vacuum seal can form a leak, which accelerates the cathode contamination. See vacuum tube.
^ Since the program counter counts memory addresses and not instructions, it is incremented by the number of memory units that the instruction word contains. In the case of simple fixed-length instruction word ISAs, this is always the same number. For example, a fixed-length 32-bit instruction word ISA that uses 8-bit memory words would always increment the PC by 4 (except in the case of jumps). ISAs that use variable length instruction words, such as x86, increment the PC by the number of memory words corresponding to the last instruction's length. Also, note that in more complex CPUs, incrementing the PC does not necessarily occur at the end of instruction execution. This is especially the case in heavily pipelined and superscalar architectures (see the relevant sections below).
^ Because the instruction set architecture of a CPU is fundamental to its interface and usage, it is often used as a classification of the "type" of CPU. For example, a "PowerPC CPU" uses some variant of the PowerPC ISA. Some CPUs, like the Intel Itanium, can actually interpret instructions for more than one ISA; however this is often accomplished by software means rather than by designing the hardware to directly support both interfaces. (See emulator)
^ Some early computers like the Harvard Mark I did not support any kind of "jump" instruction, effectively limiting the complexity of the programs they could run. It is largely for this reason that these computers are often not considered to contain a CPU proper, despite their close similarity as stored program computers.
^ This description is, in fact, a simplified view even of the Classic RISC pipeline. It largely ignores the important role of CPU cache, and therefore the access stage of the pipeline. See the respective articles for more details.
^ The physical concept of voltage is an analog one by its nature, practically having an infinite range of possible values. For the purpose of physical representation of binary numbers, set ranges of voltages are defined as one or zero. These ranges are usually influenced by the circuit designs and operational parameters of the switching elements used to create the CPU, such as a transistor's threshold level.
^ While a CPU's integer size sets a limit on integer ranges, this can (and often is) overcome using a combination of software and hardware techniques. By using additional memory, software can represent integers many magnitudes larger than the CPU can. Sometimes the CPU's ISA will even facilitate operations on integers larger that it can natively represent by providing instructions to make large integer arithmetic relatively quick. While this method of dealing with large integers is somewhat slower than utilizing a CPU with higher integer size, it is a reasonable trade-off in cases where natively supporting the full integer range needed would be cost-prohibitive. See Arbitrary-precision arithmetic for more details on purely software-supported arbitrary-sized integers.
^ In fact, all synchronous CPUs use a combination of sequential logic and combinatorial logic. (See boolean logic)
^ One notable late CPU design that uses clock gating is that of the IBM PowerPC-based Xbox 360. It utilizes extensive clock gating in order to reduce the power requirements of the aforementioned videogame console it is used in. (Brown 2005)
^ Neither ILP nor TLP is inherently superior over the other; they are simply different means by which to increase CPU parallelism. As such, they both have advantages and disadvantages, which are often determined by the type of software that the processor is intended to run. High-TLP CPUs are often used in applications that lend themselves well to being split up into numerous smaller applications, so-called "embarrassingly parallel problems." Frequently, a computational problem that can be solved quickly with high TLP design strategies like SMP take significantly more time on high ILP devices like superscalar CPUs, and vice versa.
^ Best-case scenario (or peak) IPC rates in very superscalar architectures are difficult to maintain since it is impossible to keep the instruction pipeline filled all the time. Therefore, in highly superscalar CPUs, average sustained IPC is often discussed rather than peak IPC.
^ Earlier the term scalar was used to compare the IPC (instructions per cycle) count afforded by various ILP methods. Here the term is used in the strictly mathematical sense to contrast with vectors. See scalar (mathematics) and vector (spatial).
^ Although SSE/SSE2/SSE3 have superseded MMX in Intel's general purpose CPUs, later IA-32 designs still support MMX. This is usually accomplished by providing most of the MMX functionality with the same hardware that supports the much more expansive SSE instruction sets.

[edit] References

^a ^b Amdahl, G. M., Blaauw, G. A., & Brooks, F. P. Jr. (1964). "Architecture of the IBM System/360". IBM Research.
^a Brown, Jeffery (2005). Application-customized CPU design. IBM developerWorks. Retrieved on 2005-12-17.
^a Huynh, Jack (2003). The AMD Athlon XP Processor with 512KB L2 Cache pp. 6-11. University of Illinois - Urbana-Champaign. Retrieved on 2007-10-06.
^a Digital Equipment Corporation (November 1975). "LSI-11 Module Descriptions", LSI-11, PDP-11/03 user's manual, 2nd edition, Maynard, Massachusetts: Digital Equipment Corporation, 4-3.
^a Garside, J. D., Furber, S. B., & Chung, S-H (1999). "AMULET3 Revealed". University of Manchester Computer Science Department.
Hennessy, John A.; Goldberg, David (1996). Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers. ISBN 1-55860-329-8.
^a Gary D. Knott (1974) [http://doi.acm.org/10.1145/775280.775282 A proposal for certain process management and intercommunication primitives ACM SIGOPS Operating Systems Review. Volume 8 , Issue 4 (October 1974). pp. 7 - 44
^a MIPS Technologies, Inc. (2005). "MIPS32® Architecture For Programmers Volume II: The MIPS32® Instruction Set". MIPS Technologies, Inc..
^a Smotherman, Mark (2005). History of Multithreading. Retrieved on 2005-12-19.
^a von Neumann, John (1945). "First Draft of a Report on the EDVAC". Moore School of Electrical Engineering, University of Pennsylvania.
^a ^b Weik, Martin H. (1961). "A Third Survey of Domestic Electronic Digital Computing Systems". Ballistic Research Laboratories.

[edit] External links

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Microprocessor designers

Advanced Micro Devices - Advanced Micro Devices, a designer of primarily x86-compatible personal computer CPUs.
ARM Ltd - ARM Ltd, one of the few CPU designers that profits solely by licensing their designs rather than manufacturing them. ARM architecture microprocessors are among the most popular in the world for embedded applications.
Freescale Semiconductor (formerly of Motorola) - Freescale Semiconductor, designer of several embedded and SoC PowerPC based processors.
IBM Microelectronics - Microelectronics division of IBM, which is responsible for many POWER and PowerPC based designs, including many of the CPUs utilized in late video game consoles.
Intel Corp - Intel, a maker of several notable CPU lines, including IA-32, IA-64, and XScale. Also a producer of various peripheral chips for use with their CPUs.
MIPS Technologies - MIPS Technologies, developers of the MIPS architecture, a pioneer in RISC designs.
Sun Microsystems - Sun Microsystems, developers of the SPARC architecture, a RISC design.
Texas Instruments - Texas Instruments semiconductor division. Designs and manufactures several types of low power microcontrollers among their many other semiconductor products.
Transmeta - Transmeta Corporation. Creators of low-power x86 compatibles like Crusoe and Efficeon.

Further reading

Standard Performance Evaluation Corporation, a non-profit organization that provides standardized performance tests on CPU's and other computer benchmarks.
Processor Design: An Introduction - Detailed introduction to microprocessor design. Somewhat incomplete and outdated, but still worthwhile.
How Microprocessors Work

2007-11-09T08:59:00.001-08:00

Entertainment | Computer Games

Let's face it. Children with visual impairments, even more so than their sighted peers, need to use computers. Why? Because it's one of the fastest and easiest ways to have access to information. Why hire someone to read to you when you can use a screen reader to read it to yourself whenever you want?
One of the first steps for the child and their family is learning how to entertain themselves on the computer. After some fun and educational activities on the computer, you can all feel more comfortable and competent about using the computer for more utilitarian purposes like writing a book report for school or exchanging e-mail messages with friends.
On this page, I attempt to offer some advice on software for a child with visual impairments. Sometimes the advice is on what not to buy. Sometimes it will be to forewarn you on the extent to which a given program will be independently accessible to the child. And, where and as much possible, I'll try to help you learn how to get and set up these games.
PLEASE PLEASE PLEASE! If you have any comments or feedback that will make this information more helpful, accurate or complete, please let me know. If you've found out the hard way that a particular game is or is not worth getting for a visually impaired child, I'd love to add it to this list too. Send all comments and feedback to me at webmaster@viguide.com.
Introducing computers

A lot of factors contribute to how early you can introduce a child to computers: their age, their skill level and readiness, limitations imposed by their disabilities or medical condition(s), their family and school finances, educational priorities, and many many more.

Here is one person's view of how use of technology can all come together over time:

Computers running DOS as their primary operating system (286 megahertz and below) can run DOS-based games, using the built-in PC speaker for sound output. If possible, you can add a sound card to the system for $100-$150 or so to have improved sound quality.

Computers running Windows 3.1 as their primary operating system (generally 386 megahertz and above) can run DOS-based or Windows-based games. Multimedia titles are available and can be used if the PC has a sound card installed. You have to read the box on multimedia titles, however, since some run only on the Apple Macintosh (Mac) computer and some run only under the Windows95 operating system.

Newer computers that can run Windows 95 as their primary operating system (generally Pentium computers running at 75 megahertz or above, with at least 16 megabytes of RAM) have more choices since most of these computers come with a sound card already installed. Also, the additional memory that Windows95 requires makes multimedia games run better and faster.

To introduce a child to computers, start with what you can afford. The older computers mentioned first can often be found for $100-$300 from someone who's upgraded to a newer computer. The newest computers are now becoming available for under $1000. If all of these alternatives are too pricey, consider using the computer at the nearest public library.

Eventually, add assistive technology to the mixture: a screen reader (for blind children) or screen magnifier (for children with low but usable vision); a speech synthesizer, so that sounds can come out of your multimedia sound card while synthetic speech (i.e. a digitalized voice) is coming out of the speech synthesizer; text-to-Braille translation software and a braille embosser (i.e. a printer that produces printed output in Braille), if you want to produce braille output.

Initially the child can just be exposed to the computer. Choose games that hold their interest. Ask them to decide which game to play or which activities to choose within a game. Even with games that require using a mouse, position the mouse cursor and hold it still for them so they can click it. Look at the documentation that comes with the game (or its Help menu) and see if there are any commands that can be done using the keyboard alone. If so, teach a few to the child. You can also start acclimating them to the PC keyboard, noting where keys are and where their hands should be placed. (The PC Typer program mentioned below helps with this.) Child-sized keyboards are available, but I have yet to find anyone who recommends using them.

When assistive technology is first introduced, have the child "play" with the digitalized voice, adjusting its speed and pitch and developing their listening skills. Next, you may type a letter to them or a story, and have them use the appropriate commands to read aloud a line or paragraph of it. Gradually introduce more commands, after they've mastered those.

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What makes software accessible?

Factors to consider in choosing software include:
Does it have auditory appeal?
Can all or most features be accessed via the keyboard alone?
Does it use high contrast colors, or are its colors user-configurable?
Can its text be enlarged as much as is necessary to make it visible to a child with low vision?
Is the screen simple and uncluttered, or busy and confusing?
For Windows software, does it use standard menus?
Is each field on the screen labeled, and is its label in a consistent location, e.g., above the field, to the left of the field, etc.?
Is it configurable such that it can work more easily with assistive technology, e.g., customizable keystrokes, colors, etc.
Is the documentation in accessible format, e.g., audio tape, Braille, text, HTML, or even bound such that it can be scanned?

You may also want to try the Children's Software Revue site which has databases of children's software which can be searched by publisher name or what rating it was given when reviewed by the Children's Software Revue. Another site is PEPsite which has a comprehensive directory of children's software publishers and older reviews from the Children's Software Revue.

You can also subscribe to a free magazine called Audyssey which is sent via e-mail roughly every 2 months. This magazine discusses games which are accessible to people who happen to be the blind and visually impaired. Refer to V.I. Guide's Magazine Rack page for instructions on how to subscribe.

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DOS-based speech-friendly games

Listed below is a sampling of some speech-friendly games that run under DOS. Most utilize the speaker that's built into every PC. They work best with a screen reader, although that isn't necessary if sighted assistance is available.

To download the file, right-click on the link and choose Save Target As... (in Internet Explorer) or Save Link As... (in Netscape Navigator). Once it has been downloaded, the file must be expanded using an uncompress program such as PKZIP/PKUNZIP or WinZip. (These and other compression utilities can be found at http://www.tucows.com or http://www.hotfiles.com.) Once you've expanded it, look for a file containing instructions (usually entitled README.TXT).

Most of these games cost between $10 and $30. They and many other games are available from Personal Computer Systems (PCS), 551 Compton Avenue, Perth Amboy, NJ 08861; phone (908) 826-1917, or via downloading from these sites.
http://www.clark.net/pub/poehlman/readme.htm This site has a variety of speech-friendly games that can be downloaded for free. Games include: Life, Yahtzee, Black Jack, Poker, Battleship, Football, Slot Machine, Concentration, MasterMind, Roulette and more.
http://www.simcon.net/jkitchen/ This is Jim Kitchen's site. Jim is a blind computer user who writes many free speech-friendly games. Games include a program that tests your reaction time to a changing color or sound, Master Mind, a slot machine game, Battleship, and Life. He also has a number of speech-friendly programs such as a grade 2 Braille reference guide, a menu program, a calculator, an alarm clock and an address book.
ftp://ftp.outofsight.org.nz/pub/henrich/ This site has many of the same games that are the site immediately above this,
plus a few new ones like a Golf game and bible games. However, it also has many other speech-friendly (non-game) program files you can download for free as well such as alarm clocks, calculators, utilities, and a talking checkbook program.
ftp://ftp.softcon.com This site, in its Magazine, Games and Textgame directories, has a large number of speech-friendly games, interactive fiction games as well as all past issues of the Audyssey gaming magazine (see above) available for downloading. It also has the Frotz and Winfrotz interpreters necessary to play some interactive games on an IBM compatible computer (when the game was originally designed for a different type of PC or operating system).
http://user.mc.net/pb357/games_html/games.html

Battleship
Players place their battalion on a 9-by-9 grid, where rows are numbered A through I and columns are numbered 1-9. The types of ships are indicated by these abbreviations: P=PT boats, C=cruisers, D=destroyers, A=Aircraft carriers, S=Submarines and B=Battleships . You try to hit and sink your opponent's ships and he tries to do the same with yours. Hits are recorded in the grid with an "H"; Misses are recorded with an "M." S toggles sound effects on and off. F1 repeats the question/information. X toggles the display of the grid headings (A-I and 1-9)
Humbug (interactive fiction)
In interactive fiction, you take on the role of a character in the story. By typing commands at the keyboard, you (the character) takes part in the story, such as moving around, doing things and asking questions. This demo has some features (like Hints) disabled. It costs $20 to buy. Words recognized include: GO, LOOK, ASK, EXAMINE, LIST, INVENTORY PUSH, PULL, HELP, DROP, PUT, HIT, ATTACK, etc. Directions include: NORTH, SOUTH, EAST, WEST, UP & DOWN. Using just the first letter of these commands is often acceptable. You can save your position via SAVE command and then subsequently use the LOAD command to restart a game from that saved position.
ME2 Crossword Puzzle
This is a demo version of a game that allows a visually impaired user to work with existing crossword puzzles or design their own, using braille or speech output as well as sounds from a SoundBlaster-compatible sound card. Arrow keys are used to navigate between words in the puzzle. Function keys repeat parts of the screen such as the number of letters in the word, the clue lines and the help window. Escape exits the game. Pressing the Home key displays a diagram showing the current word and all words which cross it. Be sure to download the readme file for additional installation instructions.
ME2 Memory Challenge
This is a demo version of a game written for visually impaired users of all ages, including pre-school children. In this game, the player tries to match pairs of sound effects hidden behind black and white squares on the screen. Each time a pair of the same sound effect is selected, the crowd cheers and the squares turn to colored squares. In the demo, the user is limited to only correctly guessing three pairs of sounds before being required to start a new game. Be sure to download the readme file for additional installation instructions.
Monopoly
The demo is restricted to 8 rounds (roughly a turn around the board). It costs $30 to buy. You get to choose the amount of money each player starts with and each player's token. There are sound effects as the dice is rolled and the token is moved. There are several commands to recall information (who owns what, what the prices/rents are, find out how much money someone has, etc.)
PC Typing Tutor
This is a demo version of a typing tutorial designed specifically to be used with speech synthesizers, screen magnifiers and screen readers to learn, practice and improve keyboarding skills. Runs in DOS only. It supports 8 types of speech synthesizers and is keyboard-specific (i.e. function keys along top vs. side). It has simplified screen navigation, such as: F2 repeat menu or lesson title, Spacebar to read current line, F5/F6 to decrease/increase speech rate, F9/F10 to decrease/increase volume, and Alt to turn off speech.
Shooting Gallery
For 1-4 players. It supports your choice of 50 types of guns and 4 shooting ranges: (a) skeet range, where you aim at clay pigeons, (b) rifle range, where you aim at a cardboard target, (c) pistol range, where you aim at a human silhouette (d) junk yard, where what you aim at varies. Varying tones indicate where you're aiming, e.g., foot to head in pistol range). The object is to fire the gun (using the Spacebar or Enter key) when it's aimed appropriately.
Trivia 2000
This is much like Trivial Pursuit and it supports 1-6 players. You can choose how many pies it takes to win. Categories are People and Music. Simplified navigation with screen reader, mostly F1 through F6. Since an incorrect answer could be due to a typographical mistake, the game will accept retries.
VIP Gegs
This is a variety of a word scrambler game. Given 5-7 letter words, you have to guess what it spells. Also supports scrambled phrases (music phrases, movie phrases and cliches). It offers simplified navigation with a screen reader, such as arrow keys or letters to select menu options. It gives hints, although the hints are not always very helpful.
Yahtzee
For 2-9 players. It offers simplified navigation if a screen reader is used. For instance, F1, F2 and F3 read various portions of the screen. R to roll dice. Letters A-N to indicate how you want to score something. Escape to exit.

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Windows-based speech-friendly games

Listed below are some Windows-based games, along with a description of them and an indication of its accessibility.

Many of these titles are available from retailers such as CompUSA, Computer City, Toys R Us, Egghead Software, plus mail order companies such as PC Connection (1-800-800-5555 or http://www.pcconnection.com).
There is also a growing number of accessible games written for the Windows platform. These can be downloaded from http://www.gamesfortheblind.com and http://www.mindseye2.com/.
3,800 MIDI Magic (also called MIDI Magic)
Priced at a very reasonable $6.95, but available only from Cyberguys (1-800-892-1010 or http://www.cyberguys.com, as part #160-0910), this runs on Windows95 or Windows 3.1. This CD features a program that plays MIDI music files (___.MID) and contains hundreds of MIDI files as well. Through the player, you can listen to the music, change its tempo, change its instrumentation and even write your own music. Although you cannot write music without using a mouse, much of its playback capability is keyboard accessible. Also, you can play any MIDI files with this, so you can add your own favorites.
ABCs Jungle Jukebox
Priced around $20 to $25 and available from most software retailers. It runs under Windows95 or Windows 3.1. It is aimed at children aged 3 to 5. The object is to click on various hot spots to find hidden coins. Once you've found a hidden coin, you can pop it in the jukebox to play one of 3 games: Hip Hop, Jungle BeBop or Word DoWop. All games involve clicking on a letter on the jukebox, however the child can type the letter on the keyboard. Other than that, participation must be with sighted assistance.
Barnyard Rhythm and Moos
Priced around $20 to $25 and available from most software retailers. It runs under Windows95, Windows 3.1 or on the Mac. It is aimed at children aged 3 to 7. There are 3 areas to this game: a song player, music videos and exploring the farm. The first 2, while not keyboard accessible, offer very engaging music. The Exploring The Farm area involves clicking on hotspots to have sounds and songs played
Brain Quest (3 editions)
These games, priced around $24.95, are made by IBM. There are editions for 1st grade, 2nd grade and 3rd grade. The object of the game is to answer questions to provide brain power (i.e. fuel) for a family taking a trip. The questions are read aloud and when the mouse cursor hovers over each of the multiple choice answers, the answers are read as well. The categories include math, science, language arts, and social studies. One or all categories can be selected for a given game session. Among other places, these games can be purchased on-line from Big Kids Productions.
Junior Field Trip
Priced around $20 and available from most software retailers. It runs under Windows95 and Windows 3.1. It is aimed at children aged 5 through 8. In this game, you follow Buzzy the Knowledge Bug as he takes you to the jungle, the airport and the farm. Explore the areas and find out about the items, people, and animals you see. There are games areas within each area. In the Jungle, the games are Find It, Coloring Book, Jungle Jumble, Anteater Feeder and Trivia. The games are not very appealing to visually impaired children and there's no keyboard accessibility. The exploration is okay but fairly information intensive, so it may be more suitable for kids who are comfortable doing a lot of educational listening
K-Chess Elite
This chess game, sold by Ark Angles, is reportedly very speech friendly. It is priced around $39 and can be purchased over the Internet.
Kid Phonics I
Priced around $44.95 and available at most software retailers. It runs under Windows95, Windows 3.1 or on the Mac and is aimed at children aged 4 through 7. In this CD, Sound Buster and Word Builder games designed to teach sound discrimination, word building and sentence building are featured. In the Playroom, you can also hear 5 songs. This is a good example of a game that, while not accessible, can be appealing and certainly has educational value. There's also a Kid Phonics II game.
Lamb Chop Loves Music
Priced around $28 to $40 and available at Toys R Us and most software retailers. It runs under Windows95, Windows 3.1 or on the Mac. It is aimed at children in preschool through grade 3. This CD features the "Bremen Town Musicians" story read aloud, plus several musically-oriented games. It also has a Music Store where kids can learn about and listen to a wide variety of instruments. It has tremendous auditory appeal.
Living Books series
Priced around $10-30 and available at most software retailers. The titles in this series, such as Dr. Seuss's ABC, Berenstain Bears and Arthur Books, run under Windows95 or on the Mac. They are typically aimed at children in preschool through grade 3. These are books that are read to you and, while they are read to you, the words are highlighted on the screen. They also offer some degree of interactivity. With sighted assistance to "drive", a young child could find these quite appealing. Also, IntelliTools has developed an Instant Access product which makes 16 of the Living Books titles instantly accessible via an IntelliKeys keyboard or a switch.
Storybook Weaver Deluxe
Priced around $20and available at most software retailers and also at http://www.mecc.com/. It runs under Windows95, Windows 3.1 or on the Mac. It is aimed at children aged 6 through 12. In this CD, kids can write their own story and embellish it with clipart and sound clips provided (or that they create). The typed-in text can be read aloud by a built-in voice synthesizer that plays through a standard sound card. The sound quality is fairly primitive and there's no ability to add words to the dictionary to correct its pronunciation. It could be a good choice to help young children get used to a digitalized voice and a regular computer keyboard, though.
True Colors
Priced around $20 to $30 and available from http://www.odysseytales.com/. It runs under Windows95, Windows 3.1 or on the Mac. It is aimed at children in kindergarten through grade 2. In this CD, a story is read aloud (running either independently, or with the mouse used to move to the next page). There are 4 activities (Keyboarding/Spelling, Math, Rhyming, and Color Mixing). The Color Mixing is not at all accessible and the others are accessible only with sighted
assistance.
Tuneland
Priced around $20-$30. Available from most software retailers, this game runs on Windows95 and Windows 3.1. Age level is approximately preschool through kindergarten. In this CD, there are 2 components. The first, called Tuneland, is several scenes, where the user clicks on various hotspots to see animations and hear music. No keyboard accessibility except for Shift-___ combinations to move from one scene to another (Shift-M to go to the Mountain, Shift-T to go to the train station). In the other component, Tuneland Tune Player, just the music is played. While the music is terrific arrangements of about 40 nursery rhymes, the player is not keyboard accessible at all.
Winnie the Pooh and the Honey Tree storybook
Priced around $32.95 and available from most software retailers, this game runs under Windows95 or Windows 3.1. It is aimed for children aged 3 to 8. This Winnie the Pooh story is read aloud in English or Spanish, either straight-through, or with the child exploring along the way by clicking on hot spots. Some hot spots play music and some play games. It is not very accessible via the keyboard.

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Other speech-friendly games

Listed below are games which do not run on PCs. Some, for instance, are handlheld stand-alone game units that run on batteries.
LevelGames
This company sells accessible versions of classic arcade games and present a "level playing field" for players with unequal abilities. Each game contains a control panel to allow users to adjust the major games functions through a very wide range. With these features, LevelGames can be played by players of any age and almost any ability. Games include: BrickOut, Ruby Ridge, and Alien Invasion.

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Low vision accessible games

Listed below are games which offer some degree of accessibility for children with low vision
Interactive Journey series
The Interactive Journey series, by The Learning Company, (Interactive Math Journey, Interactive Reading Journey) are targeted at grades K-3. When used with a screen magnifier, it works pretty well since the screens aren't overly cluttered.

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Dictionaries and Encyclopedias

Although I don't have firsthand knowledge, threads in the GUISPEAK mailing list indicate that the American Heritage dictionary is pretty speech-friendly.

The CD-ROM Access Project, sponsored by the CPB/WGBH National Center for Accessible Media, tested 4 multimedia encyclopedias (Compton's Interactive Encyclopedia, Microsoft Encarta '97 Encyclopedia, 1997 Grolier Multimedia Encyclopedia, Encyclopaedia Britannica CD '97) and using 3 different screen readers and 2 screen magnifiers. Read their report to see how they regarded each encyclopedia's accessibility. The CD-ROM Access Project also tested a variety of educational and entertainment software (such as Infinity City, Astro Algebra, SimAnt and MathView) to determine how accessible they were when using various screen readers and screen magnifiers. Read their CD-ROM Access Analysis Finding to learn what they discovered.

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Miscellaneous Links

Accessible Games
This site offers Windows 95/98 games designed specifically for blind and visually impaired users. Most of the games have been tested to ensure their compatibility with the JAWS and Window Eyes screen readers. You can buy the games individually ($12) or in a collection of 8 on a CD ($79).
Adventure Plus CD
Disability Specialtys offers a CD containing over 390 DOS-based text games and over 60 Windows-based text games. It also contains the tools and utilities needed to allow you to create your own games! Price is $40.
Audyssey Gaming Magazine
Visit http://www.espsoftworks.com to subscribe to an online magazine that discusses computer games that are accessible (and fun!) for visually impaired users. Much of the game software can be downloaded via from Paul Henrichsen's web site.
Blade's Armoury
This is Adam Taylor's web site which contains, according to him, 'an arsenal of hints, cheats and FAQs about various games for the blind and some his personal favorite arcade and PC games.' Games discussed include Ancient Domains of Mystery (ADOM), Nethack, Master of Orion and other text adventure games. He also has a download area with current versions and patches of some of these games.
Infocom Masterpieces
This page has information on how to order collections of many of the Infocom text-based adventure games that are very hard to find. Infocom is widely believed to have been the best manufacturer of text-based games, but the popularity of those games waned when multimedia became available. The CDs cost $8.95 each, in collections according to topic: Sci-fi, fantasy, comedy, mystery and adventure. They run under DOS, Windows and the Macintosh.
Snacky Pete's Text Adventure Archive
Although not as popular with the public at large as they used to be, interactive fiction games (also known as text adventure games) usually take the form of a story where you're a participant in the story. For instance, it could be a mystery and you're the detective assigned to the case. The scene of the story is introduced and your role is made clear, and then you're on your own! It's up to you to use text "commands" to move about, ask questions, do things, etc. These games can be great fun and are especially suited to older visually impaired children! This site offers many games available to be be downloaded and run under MS-DOS.
Sound Computing CD of speech-friendly software
Sound Computing offers a CD containing a comprehensive collection of speech-friendly freeware, shareware and demo programs. The CD and its accompanying 2-track explanatory cassette is called "Top Win Extra." Although much of its contents can be downloaded from the Internet, having it all in place is a big convenience. For more information, including a full listing of the CD's contents and purchase options, send a blank message to cd@sound-computing.com.

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2007-11-08T01:10:00.001-08:00

11/04/2007

Sunday Secrets

(PostSecret is an ongoing community art project where people mail in their secrets anonymously on one side of a homemade postcard.)

-----Email Message-----
Sent: Monday, November 05, 2007 6:55 PM
Subject: "Period"

. . .even though I don't know your name or who you are, I hope to read one of your books someday. . .

-----Email Message-----
Sent: Sunday, November 04, 2007 3:21 AM
Subject: re: our kids don't know we're poor

Once I was driving up Pacific Coast Highway on my way to work on a movie set at a mansion on the beach in Malibu. It was a nice day and there was a clunker of a car driving next to me with all the windows open. It was a 'poor' Mexican family. They were all smiling and singing. The father looked kind. The kids looked happy. I saw them and hoped that someday I would be have a rich life like that.

-----Email Message-----
Sent: Sunday, October 21, 2007 10:19 AM

I feel like I've known you all in the PostSecret Community for my entire life or something - I don't know, it's weird - I feel like you've all been just out of my range of vision, just out of sight - and now the lights have revealed what was there, unseen, all along.

-----Email Message-----
Sent: Sunday, November 04, 2007 9:44 AM
Subject: re: latex gloves

I use a condom on my vibrator... ;-p

-----Email Message----
Sent: Sunday, November 04, 2007 3:55 AM
Subject: friend died, nobody helped....

you will learn how to help yourself.
it will break your heart, and it will make you strong.

-----Email Message-----
Sent: Sunday, November 04, 2007 11:07 AM

Once I found myself, I realized God was there all along.

-----Email Message-----
Sent: Monday, November 05, 2007 11:13 AM
Subject: Leaving PostSecret

frank

thank you I have my sweatheart and I don't need to keep my feelings secret anymore i can share it with my love whenever i want to :)

--------------------------------------------------------------------------------
Sent: Sunday, November 04, 2007 10:12 AM
Subject: Leaving PostSecret

Hi,

I just manually removed your email from teh list.

Thanks,
-Frank

--------------------------------------------------------------------------------
Sent: Sunday, November 04, 2007 8:13 AM
Subject: Leaving PostSecret

i would like to cancel my membership - thank you

10/29/2007

A Lifetime of Secrets

Hundreds of never-before-seen secrets arranged in loose chronological order reveal the fascinating ways our secrets change over the course of our lives and the surprising ways they remain exactly the same.

Buy A Lifetime of Secrets today from Barnes & Noble, Borders, Chapters or your favorite independent book store.

By purchasing this book today for yourself or as a gift, you are supporting this project and helping me continue to post secrets here every Sunday.

Thank you for your support,
-Frank
Buy all four PostSecret books now from Amazon

10/28/2007

New Tour Dates

FOUND vs PostSecret Charity Tour

Kansas City, MO (November 12)
St. Louis, MO (November 13)
Lexington, KY (November 14)
Indianapolis, IN (November 15)
Ann Arbor, MI (November 16)
Pittsburgh, PA (November 17)
Columbus, OH (November 18)
Asheville, NC (November 30)
Durham, NC (December 1)
Richmond, VA (December 2)
Atlanta, GA (December 3)
Birmingham, AL (December 4)
New Orleans, LA (December 5)

Order Tickets Online Here.

To host a PostSecret Event at your college contact;
The Harper Collin's Speakers Bureau

2007-11-08T00:57:00.000-08:00

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Router

From Wikipedia, the free encyclopedia

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This article is about a computer networking device. For the kind of rotating cutting tool, see wood router. For the type of network router found in many homes, see DSL router.

Cisco 1800 Router

Cisco 7600 Enterprise Routers

A router is a device that extracts the destination of a packet it receives, selects the best path to that destination, and forwards data packets to the next device along this path.^[1] They connect networks together; a LAN to a WAN for example, to access the Internet. Some units, like the Cisco 1800 (pictured), are available in both wired and wireless models.

[hide]

[edit] Function

Nortel ERS 8600

A more precise definition of a router is a computer networking device that interconnects separate logical subnets. Routers are now available in many types, though all are fundamentally doing the same job. A router is a computer whose software and hardware are usually tailored to the tasks of routing and forwarding, generally containing a specialized operating system (e.g. Cisco's IOS or Juniper Networks JunOS or Extreme Networks XOS), RAM, NVRAM, flash memory, and one or more processors. High-end routers contain many processors and specialized Application-specific integrated circuits (ASIC) and do a great deal of parallel processing. Chassis based systems like the Nortel MERS-8600 or ERS-8600 routing switch, have multiple ASICs on every module and allow for a wide variety of LAN, MAN, METRO, and WAN port technologies or other connections that are customizable.

However, with the proper software (such as XORP or Quagga), even commodity PCs can act as routers.

Routers connect with two or more logical subnets, which do not necessarily map one-to-one to the physical interfaces of the router.^[2]

The term switch or layer 3 switch or network switch often is used interchangeably with router, but switch is really a marketing term without a rigorous technical definition (though a switch is commonly understood as a network hub with switched ports, which might or might not also perform additional routing functions).

Routers operate in two different planes ^[3]:

Control Plane, in which the router learns the outgoing interface that is most appropriate for forwarding specific packets to specific destinations,
Forwarding Plane, which is responsible for the actual process of sending a packet received on a logical interface to an outbound logical interface.

Routers are like intersections whereas subnets are like streets and hosts like houses

[edit] Control Plane

Main article: Control Plane

Control Plane processing leads to the construction of what is variously called a routing table or routing information base (RIB). The RIB may be used by the Forwarding Plane to look up the outbound interface for a given packet, or, depending on the router implementation, the Control Plane may populate a separate Forwarding Information Base (FIB) with destination information. RIBs are optimized for efficient updating with control mechanisms such as routing protocols, while FIBs are optimized for the fastest possible lookup of the information needed to select the outbound interface.

The Control Plane constructs the routing table from knowledge of the up/down status of its local interfaces, from hard-coded static routes, and from exchanging routing protocol information with other routers. It is not compulsory for a router to use routing protocols to function, if for example it was configured solely with static routes. The routing table stores the best routes to certain network destinations, the "routing metrics" associated with those routes, and the path to the next hop router.

Routers do maintain state on the routes in the RIB/routing table, but this is quite distinct from not maintaining state on individual packets that have been forwarded.

[edit] Forwarding Plane (a.k.a. Data Plane)

Main article: Forwarding Plane

For the pure Internet Protocol (IP) forwarding function, router design tries to minimize the state information kept on individual packets. Once a packet is forwarded, the router should retain no more than statistical information about it. It is the sending and receiving endpoint that keeps information on such things as errored or missing packets.

Forwarding decisions can involve decisions at layers other than the IP internetwork layer or OSI layer 3. Again, the marketing term switch can be applied to devices that have these capabilities. A function that forwards based on data link layer, or OSI layer 2, information, is properly called a bridge. Marketing literature may call it a layer 2 switch. but a switch has no precise definition.

[edit] Types of routers

Cisco CRS-1 Carrier Routing System

Linksys BEFSR41 DSL Router

Routers may provide connectivity inside enterprises, between enterprises and the Internet, and inside Internet Service Providers (ISP). The largest routers (for example the Cisco CRS-1 or Juniper T1600) interconnect ISPs, are used inside ISPs, or may be used in very large enterprise networks. An example of an enterprise router would be the Cisco 7600 (pictured above). The smallest routers provide connectivity for small and home offices (for example the Linksys BEFSR41).

[edit] Routers for Internet connectivity and internal use

Routers intended for ISP and major enterprise connectivity will almost invariably exchange routing information with the Border Gateway Protocol. RFC 4098^[4] defines several types of BGP-speaking routers:

Provider Edge Router: Placed at the edge of an ISP network, it speaks external BGP (eBGP) to a BGP speaker in another provider or large enterprise Autonomous System (AS).
Subscriber Edge Router: Located at the edge of the subscriber's network, it speaks eBGP to its provider's AS(s). It belongs to an end user (enterprise) organization.
Inter-provider Border Router: Interconnecting ISPs, this is a BGP speaking router that maintains BGP sessions with other BGP speaking routers in other providers' ASes.
Core router: A router that resides within the middle or backbone of the network rather than at its periphery.

Within an ISP: Internal to the provider's AS, such a router speaks internal BGP (iBGP) to that provider's edge routers, other intra-provider core routers, or the provider's inter-provider border routers.

"Internet backbone:" The Internet does not have a clearly identifiable backbone, as did its predecessors. See default-free zone (DFZ). Nevertheless, it is the major ISPs' routers that make up what many would consider the core. These ISPs operate all four types of the BGP-speaking routers described here. In ISP usage, a "core" router is internal to an ISP, and used to interconnect its edge and border routers. Core routers may also have specialized functions in virtual private networks based on a combination of BGP and Multi-Protocol Label Switching (MPLS)^[5].

[edit] Small and Home Office (SOHO) connectivity

Main article: Residential gateway

Residential gateways (often called routers) are frequently used in homes to connect to a broadband service, such as IP over cable or DSL. A home router may allow connectivity to an enterprise via a secure Virtual Private Network.

While functionally similar to routers, residential gateways use network address translation instead of routing. Instead of connecting local computers to the remote network directly, a residential gateway must make local computers appear to be a single computer.

[edit] Enterprise Routers

All sizes of routers may be found inside enterprises. While the most powerful routers tend to be found in ISPs, academic and research facilities, as well as large businesses, may need large routers.

A three-layer model is in common use, not all of which need be present in smaller networks ^[6].

[edit] Access

Access routers, including SOHO, are located at customer sites such as branch offices that do not need hierarchical routing of their own. Typically, they are optimized for low cost.

[edit] Distribution

Distribution routers aggregate traffic from multiple access routers, either at the same site, or to collect the data streams from multiple sites to a major enterprise location. Distribution routers often are responsible for enforcing quality of service across a WAN, so they may have considerable memory, multiple WAN interfaces, and substantial processing intelligence.

They may also provide connectivity to groups of servers or to external networks. In the latter application, the router's functionality must be carefully considered as part of the overall security architecture. Separate from the router may be a Firewall or VPN concentrator, or the router may include these and other security functions.

When an enterprise is primarily on one campus, there may not be a distinct distribution tier, other than perhaps off-campus access. In such cases, the access routers, connected to LANs, interconnect via core routers.

[edit] Core

In enterprises, core router may provide a "collapsed backbone" interconnecting the distribution tier routers from multiple buildings of a campus, or large enterprise locations. They tend to be optimized for high bandwidth.

When an enterprise is widely distributed with no central location(s), the function of core routing may be subsumed by the WAN service to which the enterprise subscribes, and the distribution routers become the highest tier.

[edit] History

The very first device that had fundamentally the same functionality as a router does today, i.e a packet switch, was the Interface Message Processor (IMP); IMPs were the devices that made up the ARPANET, the first packet switching network. The idea for a router (although they were called "gateways" at the time) initially came about through an international group of computer networking researchers called the International Network Working Group (INWG). Set up in 1972 as an informal group to consider the technical issues involved in connecting different networks, later that year it became a subcommittee of the International Federation for Information Processing. ^[7]

These devices were different from most previous packet switches in two ways. First, they connected dissimilar kinds of networks, such as serial lines and local area networks. Second, they were connectionless devices, which had no role in assuring that traffic was delivered reliably, leaving that entirely to the hosts (although this particular idea had been previously pioneered in the CYCLADES network).

The idea was explored in more detail, with the intention to produce real prototype system, as part of two contemporaneous programs. One was the initial DARPA-initiated program, which created the TCP/IP architecture of today. ^[8] The other was a program at Xerox PARC to explore new networking technologies, which produced the PARC Universal Packet system, although due to corporate intellectual property concerns it received little attention outside Xerox until years later. ^[9]

The earliest Xerox routers came into operation sometime after early 1974. The first true IP router was developed by Virginia Strazisar at BBN, as part of that DARPA-initiated effort, during 1975-1976. By the end of 1976, three PDP-11-based routers were in service in the experimental prototype Internet. ^[10]

The first multiprotocol routers were independently created by staff researchers at MIT and Stanford in 1981; the Stanford router was done by William Yeager, and the MIT one by Noel Chiappa; both were also based on PDP-11s. ^[11] ^[12] ^[13] ^[14]

As virtually all networking now uses IP at the network layer, multiprotocol routers are largely obsolete, although they were important in the early stages of the growth of computer networking, when several protocols other than TCP/IP were in widespread use. Routers that handle both IPv4 and IPv6 arguably are multiprotocol, but in a far less variable sense than a router that processed AppleTalk, DECnet, IP, and Xerox protocols.

In the original era of routing (from the mid-1970s through the 1980s), general-purpose mini-computers served as routers. Although general-purpose computers can perform routing, modern high-speed routers are highly specialized computers, generally with extra hardware added to accelerate both common routing functions such as packet forwarding and specialised functions such as IPsec encryption.

Still, there is substantial use of Linux and Unix machines, running open source routing code, for routing research and selected other applications. While Cisco's operating system was independently designed, other major router operating systems, such as those from Juniper Networks and Extreme Networks, are extensively modified but still have Unix ancestry.

Other changes also improve reliability, such as redundant control processors with stateful failover, and using storage having no moving parts for program loading. As much reliability comes from operational techniques for running critical routers as it does to the router design itself. It is the best common practice, for example, to use redundant uninterruptible power supplies for all critical network elements, with generator backup for the batteries or flywheels of those power supplies.

[edit] See also

[edit] External links

Look up router in Wiktionary, the free dictionary.

[edit] References

^ How Routers Work?,Curt Franklin, Accessed June 22, 2007.
^ Requirements for IPv4 Routers,RFC 1812, F. Baker,June 1995
^ Requirements for Separation of IP Control and Forwarding,RFC 3564, H. Khosravi & T. Anderson,November 2003
^ Terminology for Benchmarking BGP Device Convergence in the Control Plane,RFC 4098, H. Berkowitz et al.,June 2005
^ BGP/MPLS VPNs,RFC 2547, E. Rosen and Y. Rekhter,April 2004
^ Oppenheimer, Priscilla (2004). Top-Down Network Design. Indianapolis: Cisco Press. ISBN 1587051524.
^ Davies, Shanks, Heart, Barker, Despres, Detwiler, and Riml, "Report of Subgroup 1 on Communication System", INWG Note #1.
^ Vinton Cerf, Robert Kahn, "A Protocol for Packet Network Intercommunication", IEEE Transactions on Communications, Volume 22, Issue 5, May 1974, pp. 637 - 648.
^ David Boggs, John Shoch, Edward Taft, Robert Metcalfe, "Pup: An Internetwork Architecture", IEEE Transactions on Communications, Volume 28, Issue 4, April 1980, pp. 612- 624.
^ Craig Partridge, S. Blumenthal, "Data networking at BBN"; IEEE Annals of the History of Computing, Volume 28, Issue 1; January-March 2006.
^ Valley of the Nerds: Who Really Invented the Multiprotocol Router, and Why Should We Care?, Public Broadcasting Service, Accessed August 11, 2007.
^ Router Man, NetworkWorld, Accessed June 22, 2007.
^ David D. Clark, "M.I.T. Campus Network Implementation", CCNG-2, Campus Computer Network Group, M.I.T., Cambridge, 1982; pp. 26.
^ Pete Carey, "A Start-Up's True Tale: Often-told story of Cisco's launch leaves out the drama, intrigue", San Jose Mercury News, December 1, 2001.

2007-10-31T15:30:00.000-07:00

Space Shuttle

NASA's Space Shuttle, officially called Space Transportation System (STS), is the spacecraft currently used by the United States government for its human spaceflight missions. At launch, it consists of a rust-colored external tank (ET), two white, slender solid rocket boosters (SRBs), and a winged orbiter (the space shuttle in the narrow sense). The orbiter carries astronauts and payload such as satellites or space station parts into low earth orbit. Usually, five to seven astronauts ride in the orbiter. The payload capacity is 50,000 lb (22,700 kg). When the orbiter's mission is complete, it fires its orbital maneuvering thrusters to drop out of orbit and re-enters the Earth's atmosphere. During the descent and landing, the shuttle orbiter acts as a glider and makes a completely unpowered ("dead stick") landing. Five spaceworthy orbiters were built, of which three remain.

The Shuttle is the first orbital spacecraft designed for partial reusability. It carries payloads to low Earth orbit, provides crew rotation for the International Space Station (ISS), and performs servicing missions. The orbiter can also recover satellites and other payloads from orbit and return them to Earth, but this capacity has not been used often. However, it has been used to return large payloads from the ISS to Earth, as the Russian Soyuz spacecraft has limited capacity for return payloads. Each Shuttle was designed for a projected lifespan of 100 launches or 10 years' operational life. The man responsible for the design of the STS was Maxime Faget, who had also overseen the Mercury, Gemini and Apollo spacecraft designs. The crucial factor in the size and shape of the Shuttle Orbiter was the requirement that it be able to accommodate the largest planned spy satellites, and have the cross-range recovery range to meet classified USAF missions requirement for a one-around abort for a polar launch. Factors involved in opting for 'reusable' solid rockets and an expendable fuel tank included the desire of the Pentagon to obtain a high-capacity payload vehicle for satellite deployment, and the desire of the Nixon administration to reduce the costs of space exploration by developing a spacecraft with reusable components.

Six shuttles have been built, five of which were spaceworthy. The first orbiter, Enterprise, was not built for actual space flight, and was used only for testing purposes. Enterprise was followed by four operational space shuttles: Columbia, Challenger, Discovery and Atlantis. Challenger was destroyed on launch in 1986, and Endeavour was built as a replacement. Columbia was destroyed on re-entry in 2003.

NASA announced in 2004 that the Space Shuttle will be retired in 2010 and replaced by the Orion, a new vehicle that is designed to take humans to the Moon and beyond.

3ds MAX 2008

Create rich and complex design visualization. Generate realistic characters for a top-selling game. Bring 3D effects to the big screen. Autodesk®
3ds Max® 2008 3D modeling, animation, and rendering software helps design visualization professionals, game developers, and visual effects artists maximize their productivity by streamlining the process of working with complex scenes.

Highlights

Achieve stunning results in less time with Autodesk® 3ds Max® software. 3ds Max 2008 dramatically improves your productivity by streamlining the process of working with complex scenes. This is achieved through significant performance improvements—in areas such as viewport interaction, interactive transform and material assignment—as well as through the addition of new, artist-friendly UI and scene management features. The release also marks the launch of Review, a toolset that delivers interactive previewing of shadows, the 3ds Max sun/sky system, and Architectural and Design material settings.

In addition, 3ds Max 2008 delivers enhanced support for complex pipelines and workflows—a new, integrated MAXScript ProEditor makes extending and customizing 3ds Max easier than ever. Plus, enhanced DWG™ file-linking and data support strengthen interoperability with applications such as AutoCAD® 2008, AutoCAD® Architecture 2008, and Revit® Architecture 2008 software products. Finally, the release contains numerous Biped improvements, including new ways of layering character motion and exporting it to game engines, as well as tools that give animators new levels of flexibility with regards to their Biped rigs.

Accelerated Performance
Scene Explorer Scene Management
Review
MAXScript ProEditor
Enhanced DWG Import
Artist-Friendly Modeling Options
Biped Enhancements
Expanded Platform Support

Routers

Router

This article is about a computer networking device. For the kind of rotating cutting tool, see wood router. For the type of network router found in many homes, see residential gateway.
Cisco 1800 Router
Cisco 1800 Router

A router is a device that determines the proper path for data to travel between different networks, and forwards data packets to the next device along this path.[1] They connect networks together; a LAN to a WAN for example, to access the Internet. Some units, like the Cisco 1800 (pictured), are available in both wired and wireless models.

Function
Nortel ERS 8600
Nortel ERS 8600

A more precise definition of a router is a computer networking device that interconnects separate logical subnets. Routers are now available in many types, though all are fundamentally doing the same job. A router is a computer whose software and hardware are usually tailored to the tasks of routing and forwarding, generally containing a specialized operating system (e.g. Cisco's IOS or Juniper Networks JunOS or Extreme Networks XOS), RAM, NVRAM, flash memory, and one or more processors. High-end routers contain many processors and specialized Application-specific integrated circuits (ASIC) and do a great deal of parallel processing. However, with the proper software (such as XORP or Quagga), even commodity PCs can act as routers.

Routers connect with two or more logical subnets, which do not necessarily map one-to-one to the physical interfaces of the router.[2]

The term switch or layer 3 switch or network switch often is used interchangeably with router, but switch is really a marketing term without a rigorous technical definition (though a switch is commonly understood as a network hub with switched ports, which might or might not also perform additional routing functions).

Chassis systems like the Nortel MERS-8600 or ERS-8600 routing switch, allow for a wide variety of LAN, MAN, METRO, and WAN port technologies or other connections that are customizable.

Routers operate in two different planes [3]:

* Control Plane, in which the router learns the outgoing interface that is most appropriate for forwarding specific packets to specific destinations,
* Forwarding Plane, which is responsible for the actual process of sending a packet received on a logical interface to an outbound logical interface.

Routers are like intersections whereas subnets are like streets and hosts like houses
Routers are like intersections whereas subnets are like streets and hosts like houses

Control Plane processing leads to the construction of what is variously called a routing table or routing information base (RIB). The RIB may be used by the Forwarding Plane to look up the outbound interface for a given packet, or, depending on the router implementation, the Control Plane may populate a separate Forwarding Information Base (FIB) with destination information. RIBs are optimized for efficient updating with control mechanisms such as routing protocols, while FIBs are optimized for the fastest possible lookup of the information needed to select the outbound interface.

The Control Plane constructs the routing table from knowledge of the up/down status of its local interfaces, from hard-coded static routes, and from exchanging routing protocol information with other routers. It is not compulsory for a router to use routing protocols to function, if for example it was configured solely with static routes. The routing table stores the best routes to certain network destinations, the "routing metrics" associated with those routes, and the path to the next hop router.

Routers do maintain state on the routes in the RIB/routing table, but this is quite distinct from not maintaining state on individual packets that have been forwarded.

For the pure Internet Protocol (IP) forwarding function, router design tries to minimize the state information kept on individual packets. Once a packet is forwarded, the router should retain no more than statistical information about it. It is the sending and receiving endpoint that keeps information on such things as errored or missing packets.

Forwarding decisions can involve decisions at layers other than the IP internetwork layer or OSI layer 3. Again, the marketing term switch can be applied to devices that have these capabilities. A function that forwards based on data link layer, or OSI layer 2, information, is properly called a bridge, or layer 2 switch. A physical device called a router may also have the capability to forward based on information at other layers, if it has software that can make decisions at these other layers.

[[Image:Cisco-rs1.jpg|thumb|right|Cisco CRS-1 Carrier Routing System
Cisco 7600 Enterprise Routers
Cisco 7600 Enterprise Routers

Routers may provide connectivity inside enterprises, between enterprises and the Internet, and inside Internet Service Providers (ISP). The largest routers (for example the Cisco CRS-1 or Juniper T1600) interconnect ISPs, are used inside ISPs, or may be used in very large enterprise networks. An example of an enterprise router would be the Cisco 7600 (pictured above). The smallest routers provide connectivity for small and home offices (for example the Linksys BEFSR41).

Routers intended for ISP and major enterprise connectivity will almost invariably exchange routing information with the Border Gateway Protocol. RFC 4098[4] defines several types of BGP-speaking routers:

* Provider Edge Router: Placed at the edge of an ISP network, it speaks external BGP (eBGP) to a BGP speaker in another provider or large enterprise Autonomous System (AS).
* Subscriber Edge Router: Located at the edge of the subscriber's network, it speaks eBGP to its provider's AS(s). It belongs to an end user (enterprise) organization.
* Inter-provider Border Router: Interconnecting ISPs, this is a BGP speaking router that maintains BGP sessions with other BGP speaking routers in other providers' ASes.
* Core router: A router that resides within the middle or backbone of the network rather than at its periphery.

Within an ISP: Internal to the provider's AS, such a router speaks internal BGP (iBGP) to that provider's edge routers, other intra-provider core routers, or the provider's inter-provider border routers.
"Internet backbone:" The Internet does not have a clearly identifiable backbone, as did its predecessors. See default-free zone (DFZ). Nevertheless, it is the major ISPs' routers that make up what many would consider the core. These ISPs operate all four types of the BGP-speaking routers described here. In ISP usage, a "core" router is internal to an ISP, and used to interconnect its edge and border routers. Core routers may also have specialized functions in virtual private networks based on a combination of BGP and Multi-Protocol Label Switching (MPLS)[5].

History

The very first device that had fundamentally the same functionality as a router does today, i.e a packet switch, was the Interface Message Processor (IMP); IMPs were the devices that made up the ARPANET, the first packet switching network. The idea for a router (although they were called "gateways" at the time) initially came about through an international group of computer networking researchers called the International Network Working Group (INWG). Set up in 1972 as an informal group to consider the technical issues involved in connecting different networks, later that year it became a subcommittee of the International Federation for Information Processing. [7]

These devices were different from most previous packet switches in two ways. First, they connected dissimilar kinds of networks, such as serial lines and local area networks. Second, they were connectionless devices, which had no role in assuring that traffic was delivered reliably, leaving that entirely to the hosts (although this particular idea had been previously pioneered in the CYCLADES network).

The idea was explored in more detail, with the intention to produce an actual prototype system, as part of two contemporaneous programs. One was the initial DARPA-initiated program, which created the TCP/IP architecture of today. [8] The other was a program at Xerox PARC to explore new networking technologies, which produced the PARC Universal Packet system, although due to corporate intellectual property concerns it received little attention outside Xerox until years later. [9]

The earliest Xerox routers came into operation sometime after early 1974. The first true IP router was developed by Virginia Strazisar at BBN, as part of that DARPA-initiated effort, during 1975-1976. By the end of 1976, three PDP-11-based routers were in service in the experimental prototype Internet. [10]

The first multiprotocol routers were independently created by staff researchers at MIT and Stanford in 1981; the Stanford router was done by William Yeager, and the MIT one by Noel Chiappa; both were also based on PDP-11s. [11] [12] [13] [14]

As virtually all networking now uses IP at the network layer, multiprotocol routers are largely obsolete, although they were important in the early stages of the growth of computer networking, when several protocols other than TCP/IP were in widespread use. Routers that handle both IPv4 and IPv6 arguably are multiprotocol, but in a far less variable sense than a router that processed AppleTalk, DECnet, IP, and Xerox protocols.

In the original era of routing (from the mid-1970s through the 1980s), general-purpose mini-computers served as routers. Although general-purpose computers can perform routing, modern high-speed routers are highly specialized computers, generally with extra hardware added to accelerate both common routing functions such as packet forwarding and specialised functions such as IPsec encryption.

Still, there is substantial use of Linux and Unix machines, running open source routing code, for routing research and selected other applications. While Cisco's operating system was independently designed, other major router operating systems, such as those from Juniper Networks and Extreme Networks, are extensively modified but still have Unix ancestry.

Other changes also improve reliability, such as redundant control processors with stateful failover, and using storage having no moving parts for program loading. As much reliability comes from operational techniques for running critical routers as it does to the router design itself. It is the best common practice, for example, to use redundant uninterruptible power supplies for all critical network elements, with generator backup for the batteries or flywheels of those power supplies.

A router is an Intermediate System (IS) which operates at the network layer of the OSI reference model. Routers may be used to connect two or more IP networks, or an IP network to an internet connection.

A router consists of a computer with at least two network interface cards supporting the IP protocol. The router receives packets from each interface via a network interface and forwards the received packets to an appropriate output network interface. Received packets have all link layer protocol headers removed, and transmitted packets have a new link protocol header added prior to transmission.

The router uses the information held in the network layer header (i.e. IP header) to decide whether to forward each received packet, and which network interface to use to send the packet. Most packets are forwareded based on the packet's IP destination address, along with routing information held within the router in a routing table. Before a packet is forwarded, the processor checks the Maximum Transfer Unit (MTU) of the specified interface. Packets larger than the interface's MTU must be fragmented by the router into two or more smaller packets. If a packet is received which has the Don't Fragment (DF) bit set in the packet header, the packet is not fragmented, but instead discarded. In this case, an ICMP error message is returned to the sender (i.e. to the original packet's IP source address) informing it of the interface's MTU size. This forms the basis for Path MTU discovery (PMTU).

The routing and filter tables resemble similar tables in link layer bridges and switches. Except, that instead of specifying link hardware addresses (MAC addresses), the router table sepcify network (IP addresses). The routing table lists known IP destination addresses with the appropraite network interface to be used to reach that destiantion. A default entry may be specified to be used for all addresses not explicitly defined in the table. A filter table may also be used to ensure that unwanted packets are discarded. The filter may be used to deny access to particular protocols or to prevent unauthorised access from remote computers by discarding packets to specified destination addresses.

A router forwards packets from one IP network to another IP network. Like other systems, it determines the IP network from the logical AND of an IP address with the associated subnetwork address mask. One execption to this rule is when a router receives an IP packet to a network broadcast address. In this case, the router discards the packet. Forwarding broadcast packet can lead to severe storms of packets, and if uncontrolled could lead to network overload.

A router introduces delay (latency) as it processes the packets it receives. The total delay observed is the sum of many components including:

Time taken to process the frame by the data link protocol
Time taken to select the correct output link (i.e. filtering and routing)
Queuing delay at the output link (when the link is busy)
Other activities which consume processor resources (computing routing tables, network management, generation of logging information)

The router queue of packets waiting to be sent also introduces a potential cause of packet loss. Since the router has a finite amount of buffer memory to hold the queue, a router which receives packets at too high a rate may experience a full queue. In this case, the router ahs no other option than to simply discard excess packets. If required, these may later be retransmitted by a transport protocol.

Architecture of a router

Routers are often used to connect together networks which use different types of links (for instance an HDLC link connecting a WAN to a local Ethernet LAN). The optimum (and maximum) packet lengths (i.e. the maximum transmission unit (MTU)) is different for different types of network. A router may therefore uses IP to provide segmentation of packets into a suitable size for transmission on a network.

Associated protocols perform network error reporting (ICMP), communication between routers (to determine appropriate routes to each destination) and remote monitoring of the router operation (network management).

The operation of a simple modern router is described on a separate page. If you want to know how the router actually works click HERE.

Neděle, 28. říjen 2007

Documents

Press release - April 18, 2005: Dual Core Era Begins, PC Makers Start Selling Intel-Based PCs
Multi-core processor press backgrounder [pdf - 26.5 KB]
Intel multi-core facts, figures and code-name decoder fact sheet [pdf - 33 KB]
Intel's first dual-core processor-based platform fact sheet [pdf - 70 KB]

��

Presentations

Intel multi-core processor press presentation [pdf - 4.42 MB]

Animation

TWO ENGINES UNDER ONE HOOD
Think of a computer chip�s core--the central processing unitor CPU--as an engine.

See animation video [mpeg, 272 MB]

In a single core processor, this �performance engine� takes in raw data and turns it into either video, movies, music, digital-photos, games, email, or other rich mulitmedia content.

In a dual-core computer chip, there are two �performance engines� that can take more data and simultaneously process the data into rich multimedia content at a faster rate.

The Processor

The processor (really a short form for microprocessor and also often called the CPU or central processing unit) is the central component of the PC. It is the brain that runs the show inside the PC. All work that you do on your computer is performed directly or indirectly by the processor. Obviously, it is one of the most important components of the PC, if not the most important. It is also, scientifically, not only one of the most amazing parts of the PC, but one of the most amazing devices in the world of technology.

The processor plays a significant role in the following important aspects of your computer system:

Performance: The processor is probably the most important single determinant of system performance in the PC. While other components also play a key role in determining performance, the processor's capabilities dictate the maximum performance of a system. The other devices only allow the processor to reach its full potential.
Software Support: Newer, faster processors enable the use of the latest software. In addition, new processors such as the Pentium with MMX Technology, enable the use of specialized software not usable on earlier machines.
Reliability and Stability: The quality of the processor is one factor that determines how reliably your system will run. While most processors are very dependable, some are not. This also depends to some extent on the age of the processor and how much energy it consumes.
Energy Consumption and Cooling: Originally processors consumed relatively little power compared to other system devices. Newer processors can consume a great deal of power. Power consumption has an impact on everything from cooling method selection to overall system reliability.
Motherboard Support: The processor you decide to use in your system will be a major determining factor in what sort of chipset you must use, and hence what motherboard you buy. The motherboard in turn dictates many facets of your system's capabilities and performance.

This section discusses many different aspects of this important component in full detail, and concludes with a look at the major processor families used on the PC platform, from the original IBM PC processors to the latest technology. Note that the explanations of how the processor works and what its characteristics are, is kept mostly separate from the information on particular processors. This is done to keep information organized and easier to find. However, I also include summary tables in each of the description sections showing how the various processors fare in that particular area. This shows the evolution of the technology and lets you more easily compare processors in various ways.

Středa, 10. říjen 2007

Switches

Multiway switching

Multiway switching is a method of connecting switches in groups so that any switch can be used to connect or disconnect the load. This is most commonly done with lighting.

Two locations

1. First method
2. Second method
3. Labelling of switch terminals

Switching a load on or off from two locations (for instance, turning a light on or off from either end of a flight of stairs) requires two SPDT switches. There are two basic methods of wiring to achieve this, and other not recommended.

In the first method, mains is fed into the common terminal of one of the switches; the switches are then connected through the L1 and L2 terminals (swapping the L1 and L2 terminals will just make the switches work the other way round), and finally a feed to the light is taken from the common of the second switch. A connects to B or C, D connects to B or C; the light is on if A connects to D, i.e. if A and D both connect to B or both connect to C.

The second method is to join the three terminals of one switch to the corresponding terminals on the other switch and take the incoming supply and the wire out to the light to the L1 and L2 terminals. Through one switch A connects to B or C, through the other also to B or C; the light is on if B connects to C, i.e. if A connects to B with one switch and to C with the other.

Wiring needed in addition to the mains network (not including protective earths):

First method:

double wire between both switches
single wire from one switch to the mains
single wire from the other switch to the load
single wire from the load to the mains

Second method:

triple wire between both switches
single wire from any position between the two switches, to the mains
single wire from any position between the two switches, to the load
single wire from the load to the mains

If the mains and the load are connected to the system of switches at one of them, then in both methods we need three wires between the two switches. In the first method one of the three wires just has to pass through the switch, which tends to be less convenient than being connected. When multiple wires come to a terminal they can often all be put directly in the terminal. When wires need to be joined without going to a terminal a crimped joint, piece of terminal block, wirenut or similar device must be used and the bulk of this may require use of a deeper backbox.

Using the first method, there are four possible combinations of switch positions: two with the light on and two with the light off.

Off	On

An unrecommended method

The unrecommended way using the hot and neutral directly

If there is a hot (a unique phase) and a neutral wire in both switches and just one wire between them where the light is connected (as in the picture), you can then solve the two way switch problem easily: just plug the hot in the top from switch, the neutral in the bottom from switch and the wire that goes to the light in the middle from the switch. This in both switches. Now you have a fully functional two way switch.

This works like the first method above: there are four possibilities and just in two of them there is a hot and a neutral connected in the poles of the light. In the other ones, both poles are neutral or hot and then no current flows because the potential difference is zero.

The advantage of this method is that it uses just one wire to the light, having a hot and neutral in both switches. The reason why this is not recommended is because in both switches there will be hot and neutral wires near to each other, which can lead to a short circuit more easily than in the other methods.

More than two locations

Three-way switching.
1. First method
2. Second method
3. Labelling of switch terminals

For more than two locations, the two cores connecting the L1 and L2 of the switches must be passed through an intermediate switch (as explained above) wired to swap them over. Any number of intermediate switches can be inserted, allowing for any number of locations.

Wiring needed in addition to the mains network (not including protective earths):

First method:

double wire along the sequence of switches
single wire from the first switch to mains
single wire from the last switch to the load
single wire (neutral) from load to mains

Second method:

double wire along the sequence of switches
single wire from first switch to last switch
single wire from anywhere between two of the switches to the mains
single wire from anywhere between the same two switches to the load
single wire (neutral) from load to mains

Using the first method, there are eight possible combinations of switch positions: four with the light on and four with the light off.

Off	On

As mentioned above, the above circuit can be extended by using multiple 4-way switches between the 3-way switches to extend switching

2007-10-30T09:09:00.000-07:00

This article is about a computer networking device. For the kind of rotating cutting tool, see wood router. For the type of network router found in many homes, see residential gateway.
Cisco 1800 Router
Cisco 1800 Router

A router is a device that determines the proper path for data to travel between different networks, and forwards data packets to the next device along this path.[1] They connect networks together; a LAN to a WAN for example, to access the Internet. Some units, like the Cisco 1800 (pictured), are available in both wired and wireless models.

Function
Nortel ERS 8600
Nortel ERS 8600

A more precise definition of a router is a computer networking device that interconnects separate logical subnets. Routers are now available in many types, though all are fundamentally doing the same job. A router is a computer whose software and hardware are usually tailored to the tasks of routing and forwarding, generally containing a specialized operating system (e.g. Cisco's IOS or Juniper Networks JunOS or Extreme Networks XOS), RAM, NVRAM, flash memory, and one or more processors. High-end routers contain many processors and specialized Application-specific integrated circuits (ASIC) and do a great deal of parallel processing. However, with the proper software (such as XORP or Quagga), even commodity PCs can act as routers.

Routers connect with two or more logical subnets, which do not necessarily map one-to-one to the physical interfaces of the router.[2]

The term switch or layer 3 switch or network switch often is used interchangeably with router, but switch is really a marketing term without a rigorous technical definition (though a switch is commonly understood as a network hub with switched ports, which might or might not also perform additional routing functions).

Chassis systems like the Nortel MERS-8600 or ERS-8600 routing switch, allow for a wide variety of LAN, MAN, METRO, and WAN port technologies or other connections that are customizable.

Routers operate in two different planes [3]:

* Control Plane, in which the router learns the outgoing interface that is most appropriate for forwarding specific packets to specific destinations,
* Forwarding Plane, which is responsible for the actual process of sending a packet received on a logical interface to an outbound logical interface.

Routers are like intersections whereas subnets are like streets and hosts like houses
Routers are like intersections whereas subnets are like streets and hosts like houses

Control Plane processing leads to the construction of what is variously called a routing table or routing information base (RIB). The RIB may be used by the Forwarding Plane to look up the outbound interface for a given packet, or, depending on the router implementation, the Control Plane may populate a separate Forwarding Information Base (FIB) with destination information. RIBs are optimized for efficient updating with control mechanisms such as routing protocols, while FIBs are optimized for the fastest possible lookup of the information needed to select the outbound interface.

The Control Plane constructs the routing table from knowledge of the up/down status of its local interfaces, from hard-coded static routes, and from exchanging routing protocol information with other routers. It is not compulsory for a router to use routing protocols to function, if for example it was configured solely with static routes. The routing table stores the best routes to certain network destinations, the "routing metrics" associated with those routes, and the path to the next hop router.

Routers do maintain state on the routes in the RIB/routing table, but this is quite distinct from not maintaining state on individual packets that have been forwarded.

For the pure Internet Protocol (IP) forwarding function, router design tries to minimize the state information kept on individual packets. Once a packet is forwarded, the router should retain no more than statistical information about it. It is the sending and receiving endpoint that keeps information on such things as errored or missing packets.

Forwarding decisions can involve decisions at layers other than the IP internetwork layer or OSI layer 3. Again, the marketing term switch can be applied to devices that have these capabilities. A function that forwards based on data link layer, or OSI layer 2, information, is properly called a bridge, or layer 2 switch. A physical device called a router may also have the capability to forward based on information at other layers, if it has software that can make decisions at these other layers.

[[Image:Cisco-rs1.jpg|thumb|right|Cisco CRS-1 Carrier Routing System
Cisco 7600 Enterprise Routers
Cisco 7600 Enterprise Routers

Routers may provide connectivity inside enterprises, between enterprises and the Internet, and inside Internet Service Providers (ISP). The largest routers (for example the Cisco CRS-1 or Juniper T1600) interconnect ISPs, are used inside ISPs, or may be used in very large enterprise networks. An example of an enterprise router would be the Cisco 7600 (pictured above). The smallest routers provide connectivity for small and home offices (for example the Linksys BEFSR41).

Routers intended for ISP and major enterprise connectivity will almost invariably exchange routing information with the Border Gateway Protocol. RFC 4098[4] defines several types of BGP-speaking routers:

* Provider Edge Router: Placed at the edge of an ISP network, it speaks external BGP (eBGP) to a BGP speaker in another provider or large enterprise Autonomous System (AS).
* Subscriber Edge Router: Located at the edge of the subscriber's network, it speaks eBGP to its provider's AS(s). It belongs to an end user (enterprise) organization.
* Inter-provider Border Router: Interconnecting ISPs, this is a BGP speaking router that maintains BGP sessions with other BGP speaking routers in other providers' ASes.
* Core router: A router that resides within the middle or backbone of the network rather than at its periphery.

Within an ISP: Internal to the provider's AS, such a router speaks internal BGP (iBGP) to that provider's edge routers, other intra-provider core routers, or the provider's inter-provider border routers.
"Internet backbone:" The Internet does not have a clearly identifiable backbone, as did its predecessors. See default-free zone (DFZ). Nevertheless, it is the major ISPs' routers that make up what many would consider the core. These ISPs operate all four types of the BGP-speaking routers described here. In ISP usage, a "core" router is internal to an ISP, and used to interconnect its edge and border routers. Core routers may also have specialized functions in virtual private networks based on a combination of BGP and Multi-Protocol Label Switching (MPLS)[5].

History

The very first device that had fundamentally the same functionality as a router does today, i.e a packet switch, was the Interface Message Processor (IMP); IMPs were the devices that made up the ARPANET, the first packet switching network. The idea for a router (although they were called "gateways" at the time) initially came about through an international group of computer networking researchers called the International Network Working Group (INWG). Set up in 1972 as an informal group to consider the technical issues involved in connecting different networks, later that year it became a subcommittee of the International Federation for Information Processing. [7]

These devices were different from most previous packet switches in two ways. First, they connected dissimilar kinds of networks, such as serial lines and local area networks. Second, they were connectionless devices, which had no role in assuring that traffic was delivered reliably, leaving that entirely to the hosts (although this particular idea had been previously pioneered in the CYCLADES network).

The idea was explored in more detail, with the intention to produce an actual prototype system, as part of two contemporaneous programs. One was the initial DARPA-initiated program, which created the TCP/IP architecture of today. [8] The other was a program at Xerox PARC to explore new networking technologies, which produced the PARC Universal Packet system, although due to corporate intellectual property concerns it received little attention outside Xerox until years later. [9]

The earliest Xerox routers came into operation sometime after early 1974. The first true IP router was developed by Virginia Strazisar at BBN, as part of that DARPA-initiated effort, during 1975-1976. By the end of 1976, three PDP-11-based routers were in service in the experimental prototype Internet. [10]

The first multiprotocol routers were independently created by staff researchers at MIT and Stanford in 1981; the Stanford router was done by William Yeager, and the MIT one by Noel Chiappa; both were also based on PDP-11s. [11] [12] [13] [14]

As virtually all networking now uses IP at the network layer, multiprotocol routers are largely obsolete, although they were important in the early stages of the growth of computer networking, when several protocols other than TCP/IP were in widespread use. Routers that handle both IPv4 and IPv6 arguably are multiprotocol, but in a far less variable sense than a router that processed AppleTalk, DECnet, IP, and Xerox protocols.

In the original era of routing (from the mid-1970s through the 1980s), general-purpose mini-computers served as routers. Although general-purpose computers can perform routing, modern high-speed routers are highly specialized computers, generally with extra hardware added to accelerate both common routing functions such as packet forwarding and specialised functions such as IPsec encryption.

Still, there is substantial use of Linux and Unix machines, running open source routing code, for routing research and selected other applications. While Cisco's operating system was independently designed, other major router operating systems, such as those from Juniper Networks and Extreme Networks, are extensively modified but still have Unix ancestry.

Other changes also improve reliability, such as redundant control processors with stateful failover, and using storage having no moving parts for program loading. As much reliability comes from operational techniques for running critical routers as it does to the router design itself. It is the best common practice, for example, to use redundant uninterruptible power supplies for all critical network elements, with generator backup for the batteries or flywheels of those power supplies.

Úterý, 25. září 2007

Space Base

Class: Manned. Type: Space Station. Destination: Space Station Orbit. Nation: USA. Agency: NASA. Manufacturer: North American, McDonnell.

Growth of Space Station into a 50 man Space Base was a required capability in the Phase B NASA Space Station studies of 1969-1970. The original core Station Module was to be used in the Base build-up several years later or was to be used as a prototype of one of the Space Base modules. Space Base would serve as a major international facility for research, applications and for the support of other space operations such as servicing unmanned satellites. The crew would be large enough to include specialists of many kinds and to minimize even more the need for astronaut-type training. The Space Base would provide nearly equal zero and artificial gravity volumes and would be configured with permanent dedicated laboratories and observatories in addition to general purpose facilities.

Both Phase B teams developed very similar concepts. Living and operation functions were centered in the rotating arms while research laboratories and observatories and applications facilities were found primarily in zero gravity hub modules or in hub sections rotating to local vertical. The most significant difference in the concepts was that one had counter-rotating artificial gravity arms while the other had a single rotating arm. The North American Rockwell single rotation arm concept had a relatively high angular momentum which provided a very stable platform. The McDonnell Douglas counter-rotating arm had zero gyroscopic stability and, therefore, would require little torque to change its attitude. No conclusive arguments favored one approach over the other.

Both concepts employed dual 50 kW nuclear reactor Brayton power generating systems deployed in a "Y" arrangement on the end of the non-rotating hub. This configuration would minimize radiation effects and would simplify maintenance and replacement operations.

The 50-man space base would have used nine of the basic 12-man space station modules. A much larger 400-man 'space hotel' could eventually be assembled from 18 modules. The space base would have been launched around 1980 to support large scale manned space activities in low Earth orbit. Smaller space stations would have been launched into geostationary and lunar orbit during the mid-/late 1970s to support manned lunar exploration. The smaller 6-crew space station module would also have housed Mars-bound astronauts in 1982-86.

An alternate space base design would have moved most of the equipment from the non-rotating weightless core segment to the rotating arms, where artificial gravity would be generated.

Crew Size: 50. Design Life: 10 years. Typical orbit: 456 km x 456 km at 55 degrees inclination. Maximum Diameter: 150.00 m (490.00 ft). Span: 10.00 m (32.00 ft). Habitable Volume: 7 000.00 m3. Mass: 1 000 000 kg (2 200 000 lb). Electrical System: Nuclear. Electric System: 50.00 average kW. Associated Launch Vehicle: Saturn V.

Space Shuttle

Universe

The Universe is defined as the summation of all particles and energy that exist and the space-time in which all events occur. Based on observations of the portion of the Universe that is observable, physicists attempt to describe the whole of space-time, including all matter and energy and events which occur, as a single system corresponding to a mathematical model.

The generally accepted scientific theory which describes the origin and evolution of the Universe is Big Bang cosmology, which describes the expansion of space from an extremely hot and dense state of unknown characteristics. The Universe underwent a rapid period of cosmic inflation that flattened out nearly all initial irregularities in the energy density; thereafter the universe expanded and became steadily cooler and less dense. Minor variations in the distribution of mass resulted in hierarchical segregation of the features that are found in the current universe; such as clusters and superclusters of galaxies. There are more than one hundred billion (1011) galaxies in the Universe,[1] each containing hundreds of billions of stars, with each star containing about 1057 atoms of hydrogen.
Contents

2007-10-24T07:51:00.001-07:00

Úterý, 25. září 2007

Space Base

Space Shuttle

Universe

2007-10-12T07:17:00.000-07:00

3D Ultra Minigolf Adventures (XBox 360)

3D Ultra Minigolf Adventures je díky své jednoduchosti mnohem přístupnější oproti dospělému golfu, ...

Předobjednávka

1 615 Kč vč. DPH / 1 357 Kč bez DPH

2007-09-18T10:21:00.000-07:00

Hawking Router H2WR54G Dangerous Security Flaw

Hawking Router H2WR54G Router

It has been reported that Hawking Router model H2W54G has a dangerous security flaw.

The Weekly Podcast Security Now with Steve Gibson ( Security Now 113 ) noted that the Hawking Wireless G Router Model H2WR54G has a wireless security flaw.

It seems that if the wireless function of the Hawking Router Model H2WR54G Wireless G model router is Disabled or "Switched Off" the router will still broadcast wireless signal .

This is even though the controls for the wireless function of the router will be "disabled " or "turned off".

The security in the router is disabled and the SSID ( Network Name) of the wireless signal is set to the SSID of "venus" ( no parenthesis in SSID). The signal and SSID are broadcast in the clear and open and with absolutely no wireless security functions - even if WEP or WPA settings were used previously.

The router will now be beaming a wide open wireless network signal. This has implications and concerns for both business and home computer networks - both in terms of data collection and network instrusion as well as fears in the area of indentity theft.

The model of the routers involved at present are

H2WR54G Revision A Boot 1.0 Run Time 108

Hawking model router HWR54G was recalled in Canada by the Canadian Government regulatory authority Industry Canada.

"The Hawkings WRT54G Wireless Router....does not comply with Industry Canada equipment certification standards and thus should not be offered for sale or used by consumers.

http://www.bestbuy.ca/marketing/hawkingrecall/en/HawkingRouterNotice.pdf?logon=&langid=EN

BestBuy in Canada has issues a recall notice for the Hawking Tech HWR54G Wireless G model Router.

Best Buy Canada November 2005 Product Recall Notice :

Recal l Notice Industry Canada has determined that the Hawking wireless G router,model HWR54G, does not comply with Industry Canada's equipmentcertification standards and thus has to be recalled immediately. If youhave purchased this model please return it to a Best Buy store withyour original invoice for a full refund.
We sincerely apologize for any inconvenience that this may cause you.Your co-operation on this is greatly appreciated.
link of recall notice :

http://www.bestbuy.ca/marketing/haw...ogon=&langid=EN

2007-09-06T08:19:00.000-07:00

3com adsl 11g cradsl72 router config.bin information disclosure

########################################
3com adsl 11g 3cradsl72 router config.bin information disclosure.
vendor url:http: www.//3com.com/
vendor notified: yes exploit avaible : yes
advisore url:http://lostmon.blogspot.com/2005/04/
3com-adsl-11g-cradsl72-router.html
dicovered by Lostmon & vIOsOnE
last update: 2005/04/02 update solution.
OSVDB ID:15181
Secunia: SA13942
########################################

A few time ago some flaws are discovered on 3com wireles cradsl72 router:
A new flaw was discovered by me and vIOsOnE A remote user can obtain
al details about configuration of the devide and all passwords (
Internet provider and router password ) without authentication.

firmware versions affected :

1.02b afected
1.05 afected
1.10 not afected

solution:

Upgrade to version 1.10 or higher, as it has been reported to fix this vulnerability.
An upgrade is required as there are no known workarounds.

exploit :

1 open your router with this address http://[target]app_sta.stm
we look the pass of the Internet provider.

2- copy and paste this URL http://[target]/cgi-bin/config.bin
and we obtain the configurations file , inside are all details about
configuration including the pass of the device.

also if you like to bypass all authentication and don´t use
a web browser you can use wget tool and get this

wget http://xxx.xxx.xxx.xxx/cgi-bin/config.bin

and with wget we need only one url to exploting this issue

thnx to estrella to be my ligth
thnx to all who day by da suuport me
thnx to vIOsOnE he is with me and investigate ;)
--
atentamente:
Lostmon (lostmon@gmail.com)
Web-Blog: http://lostmon.blogspot.com/
Data mangler of: http://www.osvdb.org

La curiosidad es lo que hace mover la mente....

moromarka

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[edit] History of CPUs

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[edit] Design and implementation

[edit] Integer range

[edit] Clock rate

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Router

From Wikipedia, the free encyclopedia

Contents

[edit] Function

[edit] Control Plane

[edit] Forwarding Plane (a.k.a. Data Plane)

[edit] Types of routers

[edit] Routers for Internet connectivity and internal use

[edit] Small and Home Office (SOHO) connectivity

[edit] Enterprise Routers

[edit] Access

[edit] Distribution

[edit] Core

[edit] History

[edit] See also

[edit] External links

[edit] References

Highlights

Neděle, 28. říjen 2007

Středa, 10. říjen 2007

Multiway switching

Two locations

An unrecommended method

More than two locations

Úterý, 25. září 2007

Úterý, 25. září 2007

Hawking Router H2WR54G Dangerous Security Flaw

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3com adsl 11g cradsl72 router config.bin information disclosure